Adding "FILE NAME" as a parameter in verilog-A module

Dear All,

I have written a Verilog-A code which writes simulation data into the file (file_name.txt).

I want to use the file name as a variable(parameter) so that I can change the file name for different instances of the module.

Could anybody please tell how it can be done ?

################################

`include "constants.vams"
`include "disciplines.vams"

module FILE_WRITE( VIN,clk_edge_rise);
 
 input VIN;
 electrical VIN,clk_edge_rise;  
 integer fp1;
integer count ;
 
 
 
 analog begin
  @(initial_step) begin
      count=0;
      
     fp1=$fopen("/home/MAT_WORK_CAD/MODULATOR/file_name.txt","w");
     
   end
   
   @(cross(V(clk_edge_rise) - Vth, dir, ttol, vtol)) begin
     count=count+1;
     
     $fwrite(fp1, "%d , %.15E\n", count,V(VIN) );
     
    end
    @(final_step) begin
      $fclose(fp1);
      
    end
    
    
  end
     
endmodule

Kind Regards,