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[Solved] MIM capacitor is not being recognized during LVS

Subrata

Hi,

I'm trying to layout a MIM capacitor wiith MT bottom plate, and AM top plate in IBM's 7RF 180nm process. Going through the design manuals, I've found the correct ways (including floating plates and/or tie downs) to connect the MIM cap to intended contacts and pins. Everything looks clean through DRC, however, LVS doesn't seem to recognize the capacitor at all.The cap is being generated using the foundry's pcell and has label on it.

I'm using IC616 and ASSURA41. If anyone has some advice, it'd be really helpful.

Thanks.

Parents

  • Hi Quek,

    Thank you so much for your response. It was indeed a problem with the rule deck. I was laying out the cap using 6 layers of metal while checking with extract rule for 7 layers. Guess I should have figured that out during DRC.

    Thank you again and have a great day.

Reply

  • Hi Quek,

    Thank you so much for your response. It was indeed a problem with the rule deck. I was laying out the cap using 6 layers of metal while checking with extract rule for 7 layers. Guess I should have figured that out during DRC.

    Thank you again and have a great day.

Children
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