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DCDC buck converter PSS/PSTB simulation for gain/phase margin check

william prince

I am newbie for spectreRF simulation. Anyone can help me check my simulation methodology correct or not? Thanks a lot.

I am going to run full schematic simulation (not veriloga model) 

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  • Frank Wiedmann
    The problem is the frequency divider in your design. If you don't need it here, remove it from the testbench. Otherwise, you must set the Beat Frequency to its output frequency.
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  • Frank Wiedmann
    The problem is the frequency divider in your design. If you don't need it here, remove it from the testbench. Otherwise, you must set the Beat Frequency to its output frequency.
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