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DCDC buck converter PSS/PSTB simulation for gain/phase margin check

william prince

I am newbie for spectreRF simulation. Anyone can help me check my simulation methodology correct or not? Thanks a lot.

I am going to run full schematic simulation (not veriloga model) 

  • Frank Wiedmann

    The PSS "Beat Frequency" (fundamental frequency) should be the switching frequency of the converter. I don't know where the 333.333 Hz come from, but you should probably remove these sources from your testbench. The most interesting frequency range is from DC up to the switching frequency. Above the switching frequency, you will see aliasing effects (see for example http://www.designers-guide.org/Forum/YaBB.pl?num=1374341507).

  • william prince

    Thanks Frank,

     

    I have removed some unnecessary source and the beat frequency is 1.1MHz now.

    Currently I couldn't complete pss simulation due to convergence problem, shall I change reltol, iabstol, etc?

    Thanks again.   

  • william prince

    Attached is my current setting. I put 150us for tstab because it is the startup time for my DCDC to reach stable VOUT. Thanks.

  • william prince

    currently I change to this setting and try to re-run

  • Frank Wiedmann
    The problem is the frequency divider in your design. If you don't need it here, remove it from the testbench. Otherwise, you must set the Beat Frequency to its output frequency.
  • william prince
    My DCDC frequency is 1.1MHz, I need another 1.1MHz/4 clock for some internal logic control. Previously I use another vpulse with 1.1MHz ant beat frequency will become 333.33Hz (auto calculation). Now I removed vpulse and use frequency divider to divide main 1.1MHz frequency (4 times) and now the beat frequency is 1.1MHz. So it is unlikely for me to remove frequency divider. Thanks.
  • Frank Wiedmann

    In this case, you must manually set the Beat Frequency to 1.1MHZ/4=275kHz. Auto Calculate does not work for frequency dividers. And you must remove the additional stages for the division by 16 that are visible in the screenshot.

  • william prince
    Thanks. Sorry, Should be 1.1MHz/2/2/2/2=68.750k. I will try this setting. I this case beat frequency is not my DCDC switching frequency (1.1MHz) , is it ok?
  • Andrew Beckett

    Yes, because your switching frequency is an integer multiple (16) of the PSS fundamental. You can fit a whole number of cycles of 1.1MHz into a cycle of 68.750kHz, which enables it to do the Fourier analysis of a periodic waveform.

    Regards,

    Andrew.

  • william prince
    Thanks. Currently I am still working with iteration/convergence problem. PSS simulation stopped when simulation almost finished (97+%). Output log file shown above thread. Please do let me know if you have any idea what can I do to solve it. Thanks.

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