DCDC buck converter PSS/PSTB simulation for gain/phase margin check

Sorry, I don't see the output file. Did you set the Beat Frequency to 68.75 kHz? Do you generate any other frequencies in your circuit? All signals in your circuit must repeat with the period of the Beat Frequency.

Ya. I already set beat frequency to 68.75kHz. In my circuit, only two frequency used. 1.1MHz is main switching frequency and 68.75kHz divided from 1.1MHz. I have tried both shooting and harmonic balanced method and still face convergence error. For both method, I set number of harmonic to 16 (68.75khz x 16 = 1.1MHz). I also tried to adjust tolerance (reltol, abstol) but it is not working. No Verilog-a model in my schematic. I also run transient analysis and DCDC output is stable. For now, maybe what I can do is only try to simplify my DCDC circuit. p/s:I am running simulation and output logfile overwritten.

How about the logic control you mentioned? Do all signals inside it repeat with the period of the Beat Frequency?

attached is part of logic. there are some frequency divider circuit in the circuit but all signals are divided either from 1.1MHz or 75kHz.

What do you need the 75 kHz for? If you don't need it for the simulation, remove it from the testbench. Otherwise, set the Beat Frequency low enough so that all signals repeat with its period (I guess I am starting to understand where the original 333.333 Hz were coming from...).

I repeat: All signals in your circuit must repeat with the period of the Beat Frequency that you specified in the PSS setup form. If that is not the case, your simulation will never converge.

opps... sorry to make you confuse. Should be 1.1MHz and 68.75kHz. 1.2MHz and 75kHz is old design, I have changed it to 1.1MHz and 68.75MHz for current design. I my current testbench, only 1.1MHz + 4 frequency divider used (68.75kHZ). I think all signals in circuit repeat with period of beat frequency.

correction

Are you really sure that all signals in your control logic repeat after 1/68.75kHz=14.54µs? When I look at your schematic, I have some doubts.

Ok. I think I have to check and study again. Those signals are used for reverse current protection, delay signal, maximum and minimum duty cycle control and so on which is not a constant frequency. I guess in this case, my full DCDC schematic can't be used for PSS simulation. I have to redraw and simplify my actual circuit by removing all unnecessary protection circuit for AC characteristic check. 

 

error log file

Dear all, thanks for the help.

 

Finally I can complete PSTB simulation by doing below actions,

1) simplified DCDC circuit by removing RCP and OCP protection circuit

2) PSS sim: Use gear2only method, errpreset use conservative

3) PSS sim: Accuracy parameter iteration =1, steadyratio=0.1

4) reltol=1e-1, iabstol=1e-9

Only concern point is the AC simulation accuracy.

I have one question here: For DCDC PSS simulation, usually I set tstab so that DCDC complete startup and output voltage stable. If tstab time is too short and DCDC output still rising (not yet stable), PSTB simulation results correct?

Thanks.