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  3. DCDC buck converter PSS/PSTB simulation for gain/phase margin...

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DCDC buck converter PSS/PSTB simulation for gain/phase margin check

william prince
william prince over 10 years ago

I am newbie for spectreRF simulation. Anyone can help me check my simulation methodology correct or not? Thanks a lot.

I am going to run full schematic simulation (not veriloga model) 

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  • Frank Wiedmann
    Frank Wiedmann over 10 years ago

    Your parameter settings are rather unusual, for example reltol is very large, so I would not trust your results too much. You should try to get convergence with standard accuracy settings (using the errpreset parameter). A larger tstab value may be required to reach this goal.

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  • william prince
    william prince over 10 years ago

    Ya. Thanks. I am trying to tighten down the tolerance again and check the point where no convergence happen.

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    The reltol setting will have no effect. With pss, errpreset sets the loosest value for a number of accuracy parameters, including reltol - so you can tighten it beyond what the errpreset sets, but not loosen it. If you look in the log file, you'll see that it's 1e-4 during the shooting phase, and 1e-3 during the tstab phase if you've used errpreset set to conservative.

    In general, it's not necessary to set tstab to be when it has fully settled. You want to get past any nonlinear startup behaviour, but if the remaining settling is pretty linear (RC type settling), then PSS should be able to find the settled steady state response. There is the ability to "detect steady state" during the tstab to allow it to shorten the tstab if it doesn't need to run any longer - this is in recent versions of MMSIM (MMSIM14.1 if my memory is correct) and on the UI in ADE in later IC616 ISRs.

    Regards,

    Andrew

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  • william prince
    william prince over 10 years ago

    Thanks a lot for the information.

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