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Parasitic extraction problem

PS90

I have made a CMOS based circuit and then developed its layout. The DRC, ERC etc. all shows no error. For parasitic extraction, i have used QRC. Still, no error shows and extraction completed successfully. But, when i see av_extracted view, only parasitics and pins are shown but no layout, because of that i am unable to do post-layout simulations. I am unable to understand this rather strange problem. So, i have attached some images of av_extracted and layout view alongwith the DRC and QRC setting on my setup. Please help in this matter.

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  • Andrew Beckett

    I moved this to the Custom IC Design forum because it's nothing to do with SKILL.

    It looks as if something is wrong with the LVS results (Assura LVS) - you don't show that. Normally Assura LVS will save the layers that it extracted the connectivity for, plus the devices, and then QRC uses this to construct the extracted view along with the parastics it extracts.

    You seem to be missing those layers. The other possibility is that they're present, but you're not displaying the layers with the "net" purpose (check the layer palette).

    Also, I'd expect to see the devices and the recognition layer for those devices.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    I moved this to the Custom IC Design forum because it's nothing to do with SKILL.

    It looks as if something is wrong with the LVS results (Assura LVS) - you don't show that. Normally Assura LVS will save the layers that it extracted the connectivity for, plus the devices, and then QRC uses this to construct the extracted view along with the parastics it extracts.

    You seem to be missing those layers. The other possibility is that they're present, but you're not displaying the layers with the "net" purpose (check the layer palette).

    Also, I'd expect to see the devices and the recognition layer for those devices.

    Regards,

    Andrew.

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