Parasitic extraction problem

I moved this to the Custom IC Design forum because it's nothing to do with SKILL.

It looks as if something is wrong with the LVS results (Assura LVS) - you don't show that. Normally Assura LVS will save the layers that it extracted the connectivity for, plus the devices, and then QRC uses this to construct the extracted view along with the parastics it extracts.

You seem to be missing those layers. The other possibility is that they're present, but you're not displaying the layers with the "net" purpose (check the layer palette).

Also, I'd expect to see the devices and the recognition layer for those devices.

Regards,

Andrew.

Hi Pushkar Srivastav

As commented by Andrew, it could be that the layers are present but are not displayed. Anyway, the missing shapes actually will not affect netlisting of the extracted view. They are only for viewing purposes. An extracted view is essentially a layout that contains schematic symbols. Only the schematic symbols in the extracted view are used during netlisting.

In Assura-Quantus flow, the shapes in the extracted view are saved using saveInterconnect cmds in the extract.rul file. E.g. the following cmd saves lvs layer "lvs_Metal1" as "dfII_M1" in the extracted view.

saveInterconnect( (lvs_Metal1 "dfII_M1") )

As the shapes are not required for netlisting, sometimes foundry developers do not include them in extract.rul file. The extracted view will still work fine but it will look strange to a user who is used to seeing the shapes.In fact, even though the extracted view looks empty, you will find that it contains a lot of schematic symbols. You will have to zoom in to different parts of the extracted view to see them because they look very small in a layout.

>>> when i see av_extracted view, only parasitics and pins are shown but no layout, because of that i am unable to do post-layout simulations
You mentioned that you can only see parasitics and pins in the extracted view and hence is unable to proceed with post layout simulations. May I know if you have tried netlisting the extracted view? Are the devices really missing in the netlist?

By the way, QRC has been re-branded as "Quantus QRC" from EXT15.1.


Best regards
Quek

Thankyou for your valuable replies.

All the DRC, LVS, ERC and QRC shows no error in my previous figures i previously posted. Infact for cross-checking, few circuit designs which already came with cadence virtuoso, i tried to run them too. Same problem is coming with them also. I have simulated "not" circuit from "mydesignlib" in cadence virtuoso 180nm technology.

I tried doing post-layout simulation after parasitic extraction. Netlisting is not including any parasitics during simulation(using config view). May be due to this error of av_extraction. Please help me to solve this problem.

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Hi Pushkar Srivastava

I think you had not provided any info on whether there are actual non-parasitic devices in the extracted view. Would you please try the following?

a. Open up the extracted view
b. Go to "Launch->ADE L"
c. Go to "ADE: Simulation->Netlist->Create"

Do you see any mos devices in the generated netlist?

Best regards
Quek