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Parasitic extraction problem

I have made a CMOS based circuit and then developed its layout. The DRC, ERC etc. all shows no error. For parasitic extraction, i have used QRC. Still, no error shows and extraction completed successfully. But, when i see av_extracted view, only parasitics and pins are shown but no layout, because of that i am unable to do post-layout simulations. I am unable to understand this rather strange problem. So, i have attached some images of av_extracted and layout view alongwith the DRC and QRC setting on my setup. Please help in this matter.

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PS90 over 10 years ago

Thankyou for your valuable replies.

All the DRC, LVS, ERC and QRC shows no error in my previous figures i previously posted. Infact for cross-checking, few circuit designs which already came with cadence virtuoso, i tried to run them too. Same problem is coming with them also. I have simulated "not" circuit from "mydesignlib" in cadence virtuoso 180nm technology.

I tried doing post-layout simulation after parasitic extraction. Netlisting is not including any parasitics during simulation(using config view). May be due to this error of av_extraction. Please help me to solve this problem.

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PS90 over 10 years ago

Thankyou for your valuable replies.

All the DRC, LVS, ERC and QRC shows no error in my previous figures i previously posted. Infact for cross-checking, few circuit designs which already came with cadence virtuoso, i tried to run them too. Same problem is coming with them also. I have simulated "not" circuit from "mydesignlib" in cadence virtuoso 180nm technology.

I tried doing post-layout simulation after parasitic extraction. Netlisting is not including any parasitics during simulation(using config view). May be due to this error of av_extraction. Please help me to solve this problem.

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