Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 17226
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Regarding gpdk045 PDK and the SOI transistor simulation in cadence

Pasupathy KR

Dear All,

I have three queries :

1. The transistors that come in gpdk045 are bulk MOSFET  or SOI MOSFET?

2. Also what is meant by "inherited BULK" for eg. in this sentence "nmos1v_3 - 1.1 volt nominal Vt NMOS transistor with inherited BULK" . I saw this sentence in this doc :

Reference Manual
Generic 45nm
Salicide 1.0V/1.8V 1P 11M
Process Design Kit
and Rule Decks (PRD)
Revision 3.5
18/JULY/2011

3. Also I think BSIMSOI provided by BSIM group is for channel lengths more than 100nm only (since its equations are derived from BSIM3v3 ). So how to simulate SOI MOSFET in cadence for a nanoscale length say 45nm.

Kindly clarify.

Thanks and Regards,

Pasupathy K.R

  • Andrew Beckett
    1. Bulk, not SOI.
    2. This means that the symbol for the device has three terminals (drain, gate, source), and that the bulk connection is controlled by a property rather than a physical pin. This is using a capability in Virtuoso called "Inherited Connections" which allow connections to be passed by property. This is primarily done to make the schematic less cluttered, particularly for more-digital transistor circuits where the bulks are commonly connected to the same node.
    3. Another model that is used for smaller geometry SOI processes is the utsoi (utsoi 1 series) and utsoi2 (utsoi 2 series). utsoi2 is the newer model. You can find some information about the model from Google, or this link:

    Regards,

    Andrew.

  • Andrew Beckett

    You may find this useful too:

    Andrew

  • Pasupathy KR

    Thank you very much for your reply Andrew.

    I have gone through the links reg. Leti-UTBSOI model. I requested them for the verilogA model. I will try it.

    Thanks,

    Pasupathy K.R

  • Andrew Beckett

    Hi Pasupathy,

    Both the Leti UTSOI and UTSOI2 models are built in to spectre. Type "spectre -h utsoi" or "spectre -h utsoi2" for more details; you shouldn't need to use a Verilog-A implementation.

    Regards,

    Andrew.

  • Pasupathy KR

    Oh ok fine .. thanks for the info ..

    But I think it is integrated into recent versions only ... It is not available in mine : spectre sub-version  11.1.0.467.isr12


    Regards,

    Pasupathy K.R

  • Andrew Beckett

    There's no good reason to use a 4 year old version of the simulator, when trying to use a recent model. I know utsoi is there in later MMSIM11.1 ISRs, but since there have been 3 major releases of MMSIM since the version you're using (with another one coming in October), you should move to something more recent. This is going to be simpler (and faster) than trying to use a VerilogA implementation of the model.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.