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M1 pins not getting extracted

lavgupta2

Hi everyone

I am doing a simple experiment by placing two parallel metal lines in the  layout view and trying to find the coupling between them like follows:  Since I am doing this in layout, and I don't have schematic to perform lvs, first I created a dummy spice file, used it to perform lvs and generate qrc data as in article 11691566 and then run qrc to extract the layout. 

The problem I am facing is that the extracted layout doesn't have any M1 pins. I created these pins to observe the coupling between signals applied across them. I have also made Vdd and gnd! lines and provided them with tap lines directly from my technology library. I am using virtuoso 6.1.6.101, assura 4.1.USR2 and QRC 14.1.2-s148 with IBM7RF technology. 

Edit: Does anybody know of a better way for simulating coupling across metal lines and then leveraging that coupler for circuit design in virtuoso? I thought of directly using rfTlinelib instead, but that library doesn't seem to have the layouts for devices. Also, I think I can't use coupledwires from cmrf7sf as I want to extend the coupled metal lines.

Thanks

Sincerely

Lav Gupta

  • Hi Lav Gupta

    Thank you very much for the detail description. Your approach is actually correct. Using parallel metal line is a standard method of checking
    coupling caps. Would you please help to provide the following info?

    a. What is the content of Assura ldb file?
    terminal>vldbToCdl design.ldb

    b. What is the distance between the parallel lines?

    c. What is the minSpacing of the metal?

    d. What is the current spice output which you had obtained from QRC?


    Best regards
    Quek

  • Hi Quek

    Thanks for the reply. Here is the information that you asked for.

    a. Content of Assura .ldb file:

    *.LDD


    .subckt subc SUBCON sub
    *.PININFO
    .ends subc

    .subckt testcoupler
    *.PININFO
    XavD206_1 avC1 avC3 subc a=2.51888e-11 l=7.28e-06 p=2.148e-05 w=3.46e-06
    .ends testcoupler

    b. The distance between the metal lines is 5um.

    c. M1 Space if atleast one M1 line width is greater than 25 um is 1.920 and I am using M1 width of 35um. Otherwise M1 to M1 space is >=0.2um.

    d. Regarding the spice file, I have not done a spice extraction yet and not very sure about it as QRC only works for av_extracted format for my pdk.

    One more thing, I have been thinking to use Sonnet for running the EM simulation and then do the extraction for the above problem as assura doesn't seem to work out for me. Also, Sonnet can be used to extract a spice netlist. What do you think about that?

    Sincerely

    Lav Gupta

  • Hi Lav Gupta

    Thanks for the info. Here are my comments:

    a. It looks like the problem lies in the Assura LVS. The pin info has not been captured during LVS.

    Your current output:
    >>> .subckt testcoupler

    Should be like this:
    .subckt testcoupler pin1 pin2 ...

    If you are using DFII pins which were created using "Create->Pins", the problem could due due to a lack of pinText and pinLayer commands in the Assura extract.rul file. You can try adding labels using an appropriate layer-purpose pair which can be recognized by the deck. E.g. some decks require you to use "M1 drawing" while other need "M1 label" or "M1 pin", etc. It depends on how the deck has been coded. Please search for "textToPin" cmds in the extract.rul file for more details.

    >>> c. c. M1 Space if atleast one M1 line width is greater than 25 um is 1.920 and I am using M1 width of 35um. Otherwise M1 to M1 space is >=0.2um.
    If the minSpacing value of M1 is only 0.2um, your metal lines should not be spaced at 5um. The max distance should be around 2um. Would you please try moving the lines closer (e.g. distance=1um), redo LVS and then redo QRC extraction? Even if the pin names are not extracted during LVS, you should be able to get the coupling caps in QRC output.

    d. You can simply select "Spice" format in the "Setup" tab in QRC form. If the pdk supports extracted view generation, it will definitely support spice generation.

    I am not familar with Sonnet but I think there is no need to change your current CAD flow. The problem is very minor and can be fixed very easily.

    Best regards
    Quek

  • Hi Quek

    Your advice worked! According to the rule deck, I should use M1 label for generating the pins though I was using M1 pins. However, there is still one weird thing. Now when I use vldbToCdl, I can only see:

    *.LDD

    Its probably because I am using dummy schematic while performing the lvs. But, when I check .erc file, I can see all the pins. And my extracted layout also has all those pins. Anyways, thanks for the help :-)

    Lav

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