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  3. M1 pins not getting extracted

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M1 pins not getting extracted

lavgupta2
lavgupta2 over 9 years ago

Hi everyone

I am doing a simple experiment by placing two parallel metal lines in the  layout view and trying to find the coupling between them like follows:  Since I am doing this in layout, and I don't have schematic to perform lvs, first I created a dummy spice file, used it to perform lvs and generate qrc data as in article 11691566 and then run qrc to extract the layout. 

The problem I am facing is that the extracted layout doesn't have any M1 pins. I created these pins to observe the coupling between signals applied across them. I have also made Vdd and gnd! lines and provided them with tap lines directly from my technology library. I am using virtuoso 6.1.6.101, assura 4.1.USR2 and QRC 14.1.2-s148 with IBM7RF technology. 

Edit: Does anybody know of a better way for simulating coupling across metal lines and then leveraging that coupler for circuit design in virtuoso? I thought of directly using rfTlinelib instead, but that library doesn't seem to have the layouts for devices. Also, I think I can't use coupledwires from cmrf7sf as I want to extend the coupled metal lines.

Thanks

Sincerely

Lav Gupta

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  • lavgupta2
    lavgupta2 over 9 years ago

    Hi Quek

    Your advice worked! According to the rule deck, I should use M1 label for generating the pins though I was using M1 pins. However, there is still one weird thing. Now when I use vldbToCdl, I can only see:

    *.LDD

    Its probably because I am using dummy schematic while performing the lvs. But, when I check .erc file, I can see all the pins. And my extracted layout also has all those pins. Anyways, thanks for the help :-)

    Lav

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  • lavgupta2
    lavgupta2 over 9 years ago

    Hi Quek

    Your advice worked! According to the rule deck, I should use M1 label for generating the pins though I was using M1 pins. However, there is still one weird thing. Now when I use vldbToCdl, I can only see:

    *.LDD

    Its probably because I am using dummy schematic while performing the lvs. But, when I check .erc file, I can see all the pins. And my extracted layout also has all those pins. Anyways, thanks for the help :-)

    Lav

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