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Problems generating layout

Hi,

I am using Virtuoso sub-version IC6.1.5.500.16.2. I have problems when I generate a layout from a schematic. In the layout, the cells appear: pcell Eval Failed.

CIW description is the following:

INFO (LX-1063): Building the layout generation form...

*WARNING* (LX-2002): Cannot create layout instance for schematic instance 'V0' because there is no layout master defined.

*WARNING* (LX-2003): Cannot create instance terminal on layout instance '|M3' because the instance master 'PRIMLIB_2113/ne3/layout' does not have a corresponding terminal 'B'.

*WARNING* (LX-2003): Cannot create instance terminal on layout instance '|M3' because the instance master 'PRIMLIB_2113/ne3/layout' does not have a corresponding terminal 'D'.

*WARNING* (LX-2003): Cannot create instance terminal on layout instance '|M3' because the instance master 'PRIMLIB_2113/ne3/layout' does not have a corresponding terminal 'G'.

*WARNING* (LX-2003): Cannot create instance terminal on layout instance '|M3' because the instance master 'PRIMLIB_2113/ne3/layout' does not have a corresponding terminal 'S'.

*WARNING* (LX-2006): There were errors or warnings during layout generation.

INFO (LX-1030): Run Connectivity - Check - Against Source for more details.

INFO (LCE-1006): Cellview 'PRIMLIB_2113/pe3/layout' is extracted using technology library 'TECH_XC018_2113' from the top level cellview and not its attached technology library 'cdsDefTechLib'.

INFO (LCE-1006): Cellview 'PRIMLIB_2113/ne3/layout' is extracted using technology library 'TECH_XC018_2113' from the top level cellview and not its attached technology library 'cdsDefTechLib'.

INFO (LCE-1009): The cell verifier found no violations.

Rafael,

Thanks

Parents

Andrew Beckett over 9 years ago

You can find out more by using Verify->Marker->Explain and then clicking on the instance with the problem.

Regards,

Andrew
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Andrew Beckett over 9 years ago

You can find out more by using Verify->Marker->Explain and then clicking on the instance with the problem.

Regards,

Andrew
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monkeydliren over 6 years ago in reply to Andrew Beckett

Hi Andrew, thanks for pointing out this useful tool.

I am not sure what happened with rafaelon, but i got a similar error in layout xl as well when generating all from source, my issue was i included parameters in transistor width, which the layout editor cannot interpret, after i changed those parameters to the actual number, everything is working fine.

Hopefully this can be helpful for anyone that might have some similar issue in the future
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