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parametrized netlist generation at scale

miwe

Dear Cadence Forum,

for an evaluation of different implementation variants of a design I am working on, I would like to use a hierarchical pPar parameter to select which cell I want to use for a simulation. As a simplified example, I'd like to use parameter pPar("driving_strength") to select an instance of a gate from a given set (i.e. standard cell library) of gates with differently sized output stages.

I would like to do analog transient simulations with that; up to now, I've been using spectre for this purpose.

What I have tried so far:

1. I have created a cellview with all possible cells being connected in parallel through "ideal switches" at the input and output. As ideal switches, I used "switch" from spectre (Cadende name "sp1tswitch", "sp2tswitch", ... from "analogLib") and configured the switch positions in the following manner:

(pPar(...) == expected_value) ? 1 : 0

This works, the results are as expected, but the spectre performance does not seem to scale well. For example, in a simple case with two parameters having four possible values each, simulating all sixteen possible combinations takes less than five minutes -- but when parameter one has a set of ten possible values and parameter two has a set of 20 possible values, even the simulation for one single point takes around 30 minutes.

2. The first approach left the unused branches disconnected, i.e. floating. In a second approach, I connected all unused inputs as well as outputs to a defined voltage (i.e. VDD or GND depending on use case), but did not notice a significant performance improvement.

3. I had a brief look at VerilogA and VerilogAMS to see whether I can use some "switch/case" or "if/else" for conditional instantitation of instances.

3a. As far as I am aware, VerilogA does not support conditional generation of instances -- or am I on the wrong track?

3b. For VerilogAMS, I generated the following code:

`include "constants.vams"
`include "disciplines.vams"

module VarDrivingStrengthGate ( in, out );
  input in;
  output out;
parameter real driving_strength = 0 ;

generate
  if (driving_strength == 1)
    STDCELL_GATE1 instanceGate(in, out);
  if (driving_strength == 2)
    STDCELL_GATE2 instanceGate(in, out);
endgenerate

endmodule

The module seems to be parsed correctly, I see that for example in the hierarchy editor that maps STDCELL_GATE1 and STDCELL_GATE2 to the correct cellviews. However, I could not get the simulation running. I tried:

3b.1 create "config" cellview, open with Hierarchy Editor, add Stop and View List (basically copy from spectre settings, add 'verilogams' to View List), select testbench schematic.

3b.2 create "adexl" cellview, create test, select "config" cellview to be simulated, select "spectreVerilog" as simulator.

3b.3 netlist creation aborts with an error, the logfile contains the following info:

\o spectreVerilog import netlist enabled
\o design has changed ... import netlist file deleted
\o partition...
\o *USRERR: During design partitioning, the partitioner failed to identify
\o "Model VarDrivingStrengthGate, lib MyLibrary, view verilogams" as analog, digital or mixed-signal.
\o This happens because view schematic is not included in either digital or analog stop-lists.
\o Verify the following lists in the stated order:
\o switch-list
\o stop-view list
\o analog stop-view list
\o digital stop-view list.
\e *Error* Failed to partition the design.
\e
\o       ...unsuccessful.
\o ERROR (ADE-3010): Cannot create and partition the design.

Questions

  • Am I on the right track using VerilogAMS "if/else" or "switch/case" statements to create pPar-dependent netlists?
  • What alternatives are there to create pPar-dependent netlists that scale well with the number of possible values?
  • If VerilogAMS is the way to go, can anyone give me a hint about what could have gone wrong in 3b?

I've spent quite some time on this issue and appreciate your help very much!

Best regards,
Michael Weiner

Cadence IC6.1.5-64b.500.132

  • Andrew Beckett

    Michael,

    This is not really a supported approach so it doesn't surprise me that you've hit numerous obstacles along the way. A few comments:

    1. sp1tswitch etc is not really intended for this. It's expected to be used as an analysis-dependent switch - and even that should be used with caution. In your case since you have all of your circuits present, the simulator is having to solve the entire circuit - and if you have some of the circuits that are essentially floating, that is probably going to lead to convergence difficulties (as well as having a bigger matrix to solve anyway).
    2. Doing view switching with parameters is an idea that we moved away from when we moved from 4.3.4 to 4.4 (in 1995/1996) when the hierarchy editor was introduced. The idea was that configuration of the design should be separate from the schematic hierarchy, because that way you can configure which views are used without needing to modify the schematics. 
    3. Spectre supports conditional inclusion of instances, but there's no netlister support for this. It would need spectre if statements in the netlist around the instances you want to include.
    4. Verilog A/AMS etc do not support conditional inclusion of instances
    5. An approach that you could take is to use the Add Config Sweep that was added in IC616 (ISR11, I think) - I'll outline that below

    For the Add Config Sweep, the idea is that you can add a new global variable in ADE XL which allows a view to be swept - effectively switching to use different views for a block in the simulation. Here's how you do it:

    First use the context (Right Mouse Button) menu over the global variables to add a new config sweep:

    Then a form will appear:

    List the views you want to sweep over (you can change this later)

    The Data View will now look like this:

    It's treated like another sweep variable - you can reference the variable in the corners UI too once you've created it here. You can also click on the variable value section and click on the "..." button when that appears to change the views (or just type in the list).

    This is much cleaner than trying to do it with pPar - I can't quite see why you'd want to do it that way anyway?

    Regards,

    Andrew.

  • miwe

    Dear Andrew,

    thank you very much for your detailed reply.

    To come to your last question, I only had known pPar as "sweep variable", that is why I was explicitly mentioning pPar.  (One of) the *actual* goals I want to achieve is avoid copying the complete design hierarchy starting from the top-level testbench going down to the cell that instantiates the gates I for each possible gate variant I want to evaluate. This approach had been time-consuming and error prone.

    Unfortunately, the university I am working at has not rolled out IC6.1.6 so far, so currently I am still forced to using Virtuoso 6.1.5, and did not find the menu items you mentioned in your previous post.

    As a next step (or as long as I do not have access to Cadence 6.1.6), I am trying to

    - write some scripts that modify the spectre netlists, using the automatically generated netlists as a template
    - then call spectre from command line

    unless you have some better idea. :-)

    Thank you for your help again!

    Michael

  • Andrew Beckett

    Michael,

    Another alternative is to create multiple config views, each configured to use different views of the block in question.

    Then in ADE XL copy each test multiple times and change the design to point to a different config.

    A bit clunky, bit it would work. Or just ask the university to move to IC616 (after all, it was released nearly 2.5 years ago!) and IC617 will be out shortly...

    Regards,

    Andrew.

  • miwe

    As announced, I wrote a set of tools including a netlist template processor that basically gives me all degrees of freedom that the simulator offers. I chose Python as the main language because there are many quite helpful tools for post-processing (e.g. numpy, matplotlib), and because I already had some experience with it. :-)

    I have published the tools named SALVADOR (Simulation Automation Library for Verification and Analysis of Design Operating Regions):

    https://gitlab.lrz.de/michael.weiner/salvador

    The template instantiator (instantiate) needs as inputs

    • a netlist template directory, consisting of text files, containing template parameters using the Python string formatting syntax
    • sets of values for these template parameters (JSON or Python)

    as output, one netlist instance is created for each set of input parameters.

    The template instantiation is context-free and works with any simulator as long as only text files are in the template directory.

    Some tools are spectre-specific, though, e.g. getresults that collects the results and stores it into a Python-specific format (pickle) for further processing.

    As an interesting side note: when I started running spectre from command line and began observing spectre.log, I noticed some warnings in the file that I was not aware before, e.g. about unconnected nets when I had made a mistake in the Virtuoso Schematic Editor. Therefore, the result collector tool (getresults) is not only able to extract results in form of OCEAN expressions, but also spectre statistics like number of errors/warnings/notices and run time, to identify problems in the netlist template.

    If someone else stumbles upon similar issues, I hope this provides help or at least some ideas how they can be solved in an alternative way.

    Best regards,
    Michael

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