parametrized netlist generation at scale

Dear Cadence Forum,

for an evaluation of different implementation variants of a design I am working on, I would like to use a hierarchical pPar parameter to select which cell I want to use for a simulation. As a simplified example, I'd like to use parameter pPar("driving_strength") to select an instance of a gate from a given set (i.e. standard cell library) of gates with differently sized output stages.

I would like to do analog transient simulations with that; up to now, I've been using spectre for this purpose.

What I have tried so far:

1. I have created a cellview with all possible cells being connected in parallel through "ideal switches" at the input and output. As ideal switches, I used "switch" from spectre (Cadende name "sp1tswitch", "sp2tswitch", ... from "analogLib") and configured the switch positions in the following manner:

(pPar(...) == expected_value) ? 1 : 0

This works, the results are as expected, but the spectre performance does not seem to scale well. For example, in a simple case with two parameters having four possible values each, simulating all sixteen possible combinations takes less than five minutes -- but when parameter one has a set of ten possible values and parameter two has a set of 20 possible values, even the simulation for one single point takes around 30 minutes.

2. The first approach left the unused branches disconnected, i.e. floating. In a second approach, I connected all unused inputs as well as outputs to a defined voltage (i.e. VDD or GND depending on use case), but did not notice a significant performance improvement.

3. I had a brief look at VerilogA and VerilogAMS to see whether I can use some "switch/case" or "if/else" for conditional instantitation of instances.

3a. As far as I am aware, VerilogA does not support conditional generation of instances -- or am I on the wrong track?

3b. For VerilogAMS, I generated the following code:

`include "constants.vams"
`include "disciplines.vams"

module VarDrivingStrengthGate ( in, out );
  input in;
  output out;
parameter real driving_strength = 0 ;

generate
  if (driving_strength == 1)
    STDCELL_GATE1 instanceGate(in, out);
  if (driving_strength == 2)
    STDCELL_GATE2 instanceGate(in, out);
endgenerate

endmodule

The module seems to be parsed correctly, I see that for example in the hierarchy editor that maps STDCELL_GATE1 and STDCELL_GATE2 to the correct cellviews. However, I could not get the simulation running. I tried:

3b.1 create "config" cellview, open with Hierarchy Editor, add Stop and View List (basically copy from spectre settings, add 'verilogams' to View List), select testbench schematic.

3b.2 create "adexl" cellview, create test, select "config" cellview to be simulated, select "spectreVerilog" as simulator.

3b.3 netlist creation aborts with an error, the logfile contains the following info:

\o spectreVerilog import netlist enabled
\o design has changed ... import netlist file deleted
\o partition...
\o *USRERR: During design partitioning, the partitioner failed to identify
\o "Model VarDrivingStrengthGate, lib MyLibrary, view verilogams" as analog, digital or mixed-signal.
\o This happens because view schematic is not included in either digital or analog stop-lists.
\o Verify the following lists in the stated order:
\o switch-list
\o stop-view list
\o analog stop-view list
\o digital stop-view list.
\e *Error* Failed to partition the design.
\e
\o       ...unsuccessful.
\o ERROR (ADE-3010): Cannot create and partition the design.

Questions

• Am I on the right track using VerilogAMS "if/else" or "switch/case" statements to create pPar-dependent netlists?
• What alternatives are there to create pPar-dependent netlists that scale well with the number of possible values?
• If VerilogAMS is the way to go, can anyone give me a hint about what could have gone wrong in 3b?

I've spent quite some time on this issue and appreciate your help very much!

Best regards,
Michael Weiner

Cadence IC6.1.5-64b.500.132