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Solved: binary counter in VerilogA with programmable stepsize

Clidre

Hello,

I'm modeling a binary counter in VerilogA. I defined parameter stepsize that is the desired increment.

Below the code: it has 4 bits and stepsize=3. 

I expected 0000 -> 0011 -> 0110 -> 1001 ...  BUT I get  0000 -> 0010 -> 0101 -> 1000... 

So, I got only the first increment=2 making all the following outputs wrong. Do you see what I'm doing wrong in the code? Thanks!!!

`include "constants.vams"
`include "disciplines.vams"
`define SIZE 4
module counter (out, clk);
inout clk;
electrical clk;
output [`SIZE-1 :0] out;
electrical [`SIZE-1 :0] out;
parameter integer setval = 0 from [0:(1<<`SIZE)-1];
parameter real vtrans_clk = 0.6;
parameter real vtol = 0; // signal tolerance on the clk
parameter real ttol = 0; // time tolerance on the clk
parameter real vhigh = 1.2;
parameter real vlow = 0;
parameter real tdel = 30p;
parameter real trise = 30p;
parameter real tfall = 30p;
parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
parameter integer stepsize = 3;
integer outval;
analog begin
@(initial_step("static","ac")) outval = setval;
@(cross(V(clk)-vtrans_clk,1,vtol,ttol))
outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
generate j (`SIZE-1 , 0) begin
V(out[j]) <+ transition (!!(outval &(1<<j))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
end
end
endmodule

Parents
  • Hi,

    Its awesome!!

    Works well for me. Thank you very much for sharing the code.

    I would like to add enable input signal to the counter. So whenever the enable is greater than threshold, the count up/down should go on otherwise output of the counter should be zero.

    As I dont know verilogA, i have tried to understand your code and modified it to include the enable input. Please refer the modified code below

    `include "constants.vams"
    `include "disciplines.vams"
    `define SIZE 4
    module counter (out,enable,clk);
    inout clk;
    input enable;
    electrical clk;
    electrical enable;
    output [`SIZE-1 :0] out;
    electrical [`SIZE-1 :0] out;
    parameter integer setval = 0 from [0:(1<<`SIZE)-1];
    parameter real vtrans_clk = 0.6;
    parameter real vtol = 0; // signal tolerance on the clk
    parameter real ttol = 0; // time tolerance on the clk
    parameter real vhigh = 1.2;
    parameter real vth = 1;
    parameter real vlow = 0;
    parameter real tdel = 30p;
    parameter real trise = 30p;
    parameter real tfall = 30p;
    parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
    parameter integer stepsize = 1;
    integer outval;
    analog begin
    if (V(enable)>vth)
    @(initial_step("static","ac")) outval = setval;
    @(cross(V(clk)-vtrans_clk,1,vtol,ttol))
    outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
    generate j (`SIZE-1 , 0) begin
    V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
    end
    end
    endmodule

    I am not getting any syntex error, But its generating the counter sequence irrespective of the threshold value.

    What went wrong.

    Please suggest.

    Regards,
    Vijay
Reply
  • Hi,

    Its awesome!!

    Works well for me. Thank you very much for sharing the code.

    I would like to add enable input signal to the counter. So whenever the enable is greater than threshold, the count up/down should go on otherwise output of the counter should be zero.

    As I dont know verilogA, i have tried to understand your code and modified it to include the enable input. Please refer the modified code below

    `include "constants.vams"
    `include "disciplines.vams"
    `define SIZE 4
    module counter (out,enable,clk);
    inout clk;
    input enable;
    electrical clk;
    electrical enable;
    output [`SIZE-1 :0] out;
    electrical [`SIZE-1 :0] out;
    parameter integer setval = 0 from [0:(1<<`SIZE)-1];
    parameter real vtrans_clk = 0.6;
    parameter real vtol = 0; // signal tolerance on the clk
    parameter real ttol = 0; // time tolerance on the clk
    parameter real vhigh = 1.2;
    parameter real vth = 1;
    parameter real vlow = 0;
    parameter real tdel = 30p;
    parameter real trise = 30p;
    parameter real tfall = 30p;
    parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
    parameter integer stepsize = 1;
    integer outval;
    analog begin
    if (V(enable)>vth)
    @(initial_step("static","ac")) outval = setval;
    @(cross(V(clk)-vtrans_clk,1,vtol,ttol))
    outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
    generate j (`SIZE-1 , 0) begin
    V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
    end
    end
    endmodule

    I am not getting any syntex error, But its generating the counter sequence irrespective of the threshold value.

    What went wrong.

    Please suggest.

    Regards,
    Vijay
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