Solved: binary counter in VerilogA with programmable stepsize

Update:

It works perfectly now. I post here the solution, hoping it can be helpful for future readers. The last command had a syntax error. I added a bracket between the two !! and it works now. The correct line is: 

V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);

Regards

Hi,

Its awesome!!

Works well for me. Thank you very much for sharing the code.

I would like to add enable input signal to the counter. So whenever the enable is greater than threshold, the count up/down should go on otherwise output of the counter should be zero.

As I dont know verilogA, i have tried to understand your code and modified it to include the enable input. Please refer the modified code below

`include "constants.vams"
`include "disciplines.vams"
`define SIZE 4
module counter (out,enable,clk);
inout clk;
input enable;
electrical clk;
electrical enable;
output [`SIZE-1 :0] out;
electrical [`SIZE-1 :0] out;
parameter integer setval = 0 from [0:(1<<`SIZE)-1];
parameter real vtrans_clk = 0.6;
parameter real vtol = 0; // signal tolerance on the clk
parameter real ttol = 0; // time tolerance on the clk
parameter real vhigh = 1.2;
parameter real vth = 1;
parameter real vlow = 0;
parameter real tdel = 30p;
parameter real trise = 30p;
parameter real tfall = 30p;
parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
parameter integer stepsize = 1;
integer outval;
analog begin
if (V(enable)>vth)
@(initial_step("static","ac")) outval = setval;
@(cross(V(clk)-vtrans_clk,1,vtol,ttol))
outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
generate j (`SIZE-1 , 0) begin
V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
end
end
endmodule

I am not getting any syntex error, But its generating the counter sequence irrespective of the threshold value.

What went wrong.

Please suggest.

Regards,
Vijay

Your condition is in the wrong place. It depends what you want of course - in this case I made it so that the output only goes to 0 after the next clock edge by putting the condition inside the @cross branch for the clock:

`include "constants.vams"
`include "disciplines.vams"
`define SIZE 4
module counter (out,enable,clk);
inout clk;
input enable;
electrical clk;
electrical enable;
output [`SIZE-1 :0] out;
electrical [`SIZE-1 :0] out;
parameter integer setval = 0 from [0:(1<<`SIZE)-1];
parameter real vtrans_clk = 0.6;
parameter real vtol = 0; // signal tolerance on the clk
parameter real ttol = 0; // time tolerance on the clk
parameter real vhigh = 1.2;
parameter real vth = 1;
parameter real vlow = 0;
parameter real tdel = 30p;
parameter real trise = 30p;
parameter real tfall = 30p;
parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
parameter integer stepsize = 1;
integer outval;
analog begin
  @(initial_step("static","ac")) outval = setval;
  @(cross(V(clk)-vtrans_clk,1,vtol,ttol)) begin
    if (V(enable)<vth) outval=0.0;
    else outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
  end
  generate j (`SIZE-1 , 0) begin
    V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
  end
end
endmodule

Alternatively, you could have done (I only repeated the analog block here):

analog begin
  @(initial_step("static","ac")) outval = setval;
  @(cross(V(clk)-vtrans_clk,1,vtol,ttol))
    outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
  end
  if (V(enable)<vth) outval=0.0;
 generate j (`SIZE-1 , 0) begin
   V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
 end
end
endmodule

This will return the output to 0 as soon as the enable goes low (note, I assume you're not too fussed about precisely timing the enable transition so there's no @cross for enable)

Regards,

Andrew.

Dear Andrew,

Thats great. It works well for me. Thank very much for your time and support.

Regards,
Vijay