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Solved: binary counter in VerilogA with programmable stepsize

Clidre

Hello,

I'm modeling a binary counter in VerilogA. I defined parameter stepsize that is the desired increment.

Below the code: it has 4 bits and stepsize=3. 

I expected 0000 -> 0011 -> 0110 -> 1001 ...  BUT I get  0000 -> 0010 -> 0101 -> 1000... 

So, I got only the first increment=2 making all the following outputs wrong. Do you see what I'm doing wrong in the code? Thanks!!!

`include "constants.vams"
`include "disciplines.vams"
`define SIZE 4
module counter (out, clk);
inout clk;
electrical clk;
output [`SIZE-1 :0] out;
electrical [`SIZE-1 :0] out;
parameter integer setval = 0 from [0:(1<<`SIZE)-1];
parameter real vtrans_clk = 0.6;
parameter real vtol = 0; // signal tolerance on the clk
parameter real ttol = 0; // time tolerance on the clk
parameter real vhigh = 1.2;
parameter real vlow = 0;
parameter real tdel = 30p;
parameter real trise = 30p;
parameter real tfall = 30p;
parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
parameter integer stepsize = 3;
integer outval;
analog begin
@(initial_step("static","ac")) outval = setval;
@(cross(V(clk)-vtrans_clk,1,vtol,ttol))
outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
generate j (`SIZE-1 , 0) begin
V(out[j]) <+ transition (!!(outval &(1<<j))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
end
end
endmodule

Parents

  • Your condition is in the wrong place. It depends what you want of course - in this case I made it so that the output only goes to 0 after the next clock edge by putting the condition inside the @cross branch for the clock:

    `include "constants.vams"
    `include "disciplines.vams"
    `define SIZE 4
    module counter (out,enable,clk);
    inout clk;
    input enable;
    electrical clk;
    electrical enable;
    output [`SIZE-1 :0] out;
    electrical [`SIZE-1 :0] out;
    parameter integer setval = 0 from [0:(1<<`SIZE)-1];
    parameter real vtrans_clk = 0.6;
    parameter real vtol = 0; // signal tolerance on the clk
    parameter real ttol = 0; // time tolerance on the clk
    parameter real vhigh = 1.2;
    parameter real vth = 1;
    parameter real vlow = 0;
    parameter real tdel = 30p;
    parameter real trise = 30p;
    parameter real tfall = 30p;
    parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
    parameter integer stepsize = 1;
    integer outval;
    analog begin
      @(initial_step("static","ac")) outval = setval;
      @(cross(V(clk)-vtrans_clk,1,vtol,ttol)) begin
        if (V(enable)<vth) outval=0.0;
        else outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
      end
      generate j (`SIZE-1 , 0) begin
        V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
      end
    end
    endmodule

    Alternatively, you could have done (I only repeated the analog block here):

    analog begin
      @(initial_step("static","ac")) outval = setval;
      @(cross(V(clk)-vtrans_clk,1,vtol,ttol))
        outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
      end
      if (V(enable)<vth) outval=0.0;
     generate j (`SIZE-1 , 0) begin
       V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
     end
    end
    endmodule

    This will return the output to 0 as soon as the enable goes low (note, I assume you're not too fussed about precisely timing the enable transition so there's no @cross for enable)

    Regards,

    Andrew.

Reply

  • Your condition is in the wrong place. It depends what you want of course - in this case I made it so that the output only goes to 0 after the next clock edge by putting the condition inside the @cross branch for the clock:

    `include "constants.vams"
    `include "disciplines.vams"
    `define SIZE 4
    module counter (out,enable,clk);
    inout clk;
    input enable;
    electrical clk;
    electrical enable;
    output [`SIZE-1 :0] out;
    electrical [`SIZE-1 :0] out;
    parameter integer setval = 0 from [0:(1<<`SIZE)-1];
    parameter real vtrans_clk = 0.6;
    parameter real vtol = 0; // signal tolerance on the clk
    parameter real ttol = 0; // time tolerance on the clk
    parameter real vhigh = 1.2;
    parameter real vth = 1;
    parameter real vlow = 0;
    parameter real tdel = 30p;
    parameter real trise = 30p;
    parameter real tfall = 30p;
    parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
    parameter integer stepsize = 1;
    integer outval;
    analog begin
      @(initial_step("static","ac")) outval = setval;
      @(cross(V(clk)-vtrans_clk,1,vtol,ttol)) begin
        if (V(enable)<vth) outval=0.0;
        else outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
      end
      generate j (`SIZE-1 , 0) begin
        V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
      end
    end
    endmodule

    Alternatively, you could have done (I only repeated the analog block here):

    analog begin
      @(initial_step("static","ac")) outval = setval;
      @(cross(V(clk)-vtrans_clk,1,vtol,ttol))
        outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);
      end
      if (V(enable)<vth) outval=0.0;
     generate j (`SIZE-1 , 0) begin
       V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
     end
    end
    endmodule

    This will return the output to 0 as soon as the enable goes low (note, I assume you're not too fussed about precisely timing the enable transition so there's no @cross for enable)

    Regards,

    Andrew.

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