Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 21316
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Unable to set the width of PMOS from 120nm to 60nm in 45nm Tech Library (Virtuoso Tool)

niteshtripathi

Hello Everyone,

I want to set the width of PMOS from 120nm (which is default value) to 60nm i.e. i have to divide transistor width by 2 so that i can divide a single pmos having width W into two pmos having width W/2. I am usinh 45nm tech library given by cadence itself. when i am trying to do it in properties editor it giving error that i can set the value of width below 120n. How to do it?

  • Andrew Beckett

    The CDF callbacks for this device are limiting the minimum width to 120nm as that is the minimum transistor width in this technology. A smaller size wouldn't make much sense anyway because there wouldn't be room to fit in a contact on the source or drain.

    Overriding this default would be difficult - it's coded in various places in the design kit, and you'd have to go round fixing DRC rules too.

    Why do you want to make the transistor width so small anyway?

    Of course, this is a fictional process, but even so, altering the defined rules for a technology is not something  you can normally do in real life.

    Regards,

    Andrew.

  • niteshtripathi

    sir,

    Thanks for your rply, 

    I want to set  my aspect ratio W/L=1.5. The default values of L and W in 45nm tech library is 45nm and 120nm. So for W/L=1.5, I have to decrease the value of W.

  • Andrew Beckett

    Nitesh Tripathi said:
    I want to set  my aspect ratio W/L=1.5. The default values of L and W in 45nm tech library is 45nm and 120nm. So for W/L=1.5, I have to decrease the value of W.

    So why not leave the W at default and increase the L to 80nm?

    If this was a real technology you clearly wouldn't be able to go below the minimum width, so adjusting the denominator in your ratio is the only option.

    Regards,

    Andrew

  • niteshtripathi
    sir, if i will increase or alter the value of L then still after changing the value of L, will my technology remain in 45nm
  • Andrew Beckett

    Nitesh Tripathi said:
    sir, if i will increase or alter the value of L then still after changing the value of L, will my technology remain in 45nm

    Yes, of course it will remain in 45nm. The technology sets the minimum length of your transistors, and not the other way around (i.e the length you pick cannot alter the actual technology). It's extremely common for analog design to not use minimum length transistors in a technology.

    It sounds as if you could do with a little more understanding of IC technology - I am hoping you're a student and if so, I suggest you speak to a lecturer or supervisor to get more understanding.

    Regards,

    Andrew.

  • niteshtripathi
    Thanks for your kind suggestion sir, Yes sir i am a student. I will learn those thing sir.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.