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  3. Unable to set the width of PMOS from 120nm to 60nm in 45nm...

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Unable to set the width of PMOS from 120nm to 60nm in 45nm Tech Library (Virtuoso Tool)

niteshtripathi
niteshtripathi over 9 years ago

Hello Everyone,

I want to set the width of PMOS from 120nm (which is default value) to 60nm i.e. i have to divide transistor width by 2 so that i can divide a single pmos having width W into two pmos having width W/2. I am usinh 45nm tech library given by cadence itself. when i am trying to do it in properties editor it giving error that i can set the value of width below 120n. How to do it?

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    The CDF callbacks for this device are limiting the minimum width to 120nm as that is the minimum transistor width in this technology. A smaller size wouldn't make much sense anyway because there wouldn't be room to fit in a contact on the source or drain.

    Overriding this default would be difficult - it's coded in various places in the design kit, and you'd have to go round fixing DRC rules too.

    Why do you want to make the transistor width so small anyway?

    Of course, this is a fictional process, but even so, altering the defined rules for a technology is not something  you can normally do in real life.

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    The CDF callbacks for this device are limiting the minimum width to 120nm as that is the minimum transistor width in this technology. A smaller size wouldn't make much sense anyway because there wouldn't be room to fit in a contact on the source or drain.

    Overriding this default would be difficult - it's coded in various places in the design kit, and you'd have to go round fixing DRC rules too.

    Why do you want to make the transistor width so small anyway?

    Of course, this is a fictional process, but even so, altering the defined rules for a technology is not something  you can normally do in real life.

    Regards,

    Andrew.

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