how to overwrite veriloga code in cadence

Dear all,

I use one gain control which write by verilog-A code.  After I create the symbol for the code and use it for simulation, no matter what change i did for the code, there is no change for the gain control. For example, at first I set the gain is 100, save and create the symbol, then use it for simulation, but I find this gain isn't enough, I want to change the gain to 200, but when I change the gain number in verilog-A file and save. these still no change when I simulation. I create a new one for every change, it makes me crazy.......So I want to know how to overwrite the verilog-A code instead of  create a new one in cadence.

Thanks a lot,

kind Regards.