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Verilog -A amp

black tea

I want to design an Amp in cadence by verilog-A code. I write code like blow, but I don't know how to define two input value vin_offset and vin_high. the input signal is a sine wave, the vin_offset is offset value of the sine wave, and the vin_high is the largest value of sine wave, I want to know how to define these two input value in verilog-A code. Thank you very much.

//--------------------
// amp
//
// -  amplifer
//
// sigin:    input    (val,flow)
// sigout:    output    (val,flow)
//
// INSTANCE parameters
//    gain          = gain between input and output []
//    sigin_offset  = subtracted from 'sigin' before amplification (val)
//
// MODEL parameters
//    {none}
//

module amp(sigin, sigout);
input sigin;
output sigout;
electrical sigin, sigout;
parameter real gain = 0.5/(vin_high - vin_offset);


   analog
      V(sigout) <+ gain*V(sigin) + 0.5*gain - gain*vin_offset;

endmodule



  • Andrew Beckett

    Isn't this just a matter of adding:

    parameter real vin_high=1.0;
    parameter real vin_offset=1.0;

    to the model?

    (with appropriate defaults)

    Regards,

    Andrew

  • black tea
    thanks but the signal before the amp is produced by a circuit, so the vin_offset and vin_high value is not fixed, their values will changed by the circuit~ so I want to know how to define it, thanks again
  • Andrew Beckett

    I wanted to post a picture of how this seemed to be working, but there's an issue (for me at least) in uploading pictures to forum posts (I have IT investigating). So for now, here's the code I wrote to do what you're asking. Behaviour of the gain seems a little strange to me, but the vin_high and vin_offset are being calculated on the fly from the incoming signal:

    `include "disciplines.vams"

    module amp(sigin, sigout);
    input sigin;
    output sigout;
    electrical sigin, sigout;
    //parameter real gain = 0.5/(vin_high - vin_offset);
    real vin_high,vin_offset;
    real gain;

    analog begin
      // peak input voltage so far
      vin_high=max(V(sigin),vin_high);
      // average mid-point so far (in effect)
      vin_offset=idt(V(sigin),0)/$realtime;
      // max is to ensure that you don't end up with divide by zero
      // and massive gain at start of simulation (adjust 0.1 to a reasonable
      // value)
      gain=0.5/max(vin_high-vin_offset,0.1);
      V(sigout) <+ gain*V(sigin) + 0.5*gain - gain*vin_offset;
    end

    endmodule

  • black tea
    Thanks a gain, I try this code, but still has an issue about the sine wave. Actually, the ac signal after my circuit but before the amp is a sine wave like the max value may be 0.85V and the offset value may be is 0.4V, these values changed by the input signal frequency, so I want to design an amp make the signal after my circuit can be a standard sine wave which means the max value = 1V, the offset value is 0.5V, and the frequency is not change(no matter the input signal max value is 0.85V or 0.9V or other values. Thanks
  • Andrew Beckett

    I have no idea what you're asking for. To be honest, it's far better that you determine what the model should be yourself - I was merely giving some pointers in the right direction. It sounds as if you have some kind of AGC model in mind (I don't see how the frequency can't change at the output if the input frequency does). Maybe it's just your English? The offset is pretty hard to get right unless you do some kind of long term average or a moving average - the way I showed it here was just integrating it and dividing it by the time - so the average will vary quite a lot at the beginning and settle down. You can see this in the image here: 

    n1 is the input signal (it's a sine wave which I superimposed on top of another slower sine wave to see how the offset calculation worked over time). As you can see by the pink line, the offset steadies out over time. The vin_high just follows the peak. Maybe you want more of a moving average though?

    There's an example of a moving average in a model here: 

    The same (or similar) example is in the documentation too - it's in the Cadence Verilog-A Language Reference manual in the examples chapter (Chapter 14 in MMSIM15.1).

    The netlist I used to test the model above (to produce the waveforms shown above) was:

    //

    A1 (n1 n2) amp
    V1 (n1 n3) vsource type=sine freq=1M dc=1 ampl=1
    Voffset (n3 0) vsource type=sine freq=10k dc=0 ampl=0.2
    ahdl_include "forum14.va"
    tran tran stop=200u
    save n1 n2 A1:vin_high A1:vin_offset

    Kind Regards,

    Andrew.

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