Verilog -A amp

I want to design an Amp in cadence by verilog-A code. I write code like blow, but I don't know how to define two input value vin_offset and vin_high. the input signal is a sine wave, the vin_offset is offset value of the sine wave, and the vin_high is the largest value of sine wave, I want to know how to define these two input value in verilog-A code. Thank you very much.

//--------------------
// amp
//
// -  amplifer
//
// sigin:    input    (val,flow)
// sigout:    output    (val,flow)
//
// INSTANCE parameters
//    gain          = gain between input and output []
//    sigin_offset  = subtracted from 'sigin' before amplification (val)
//
// MODEL parameters
//    {none}
//

module amp(sigin, sigout);
input sigin;
output sigout;
electrical sigin, sigout;
parameter real gain = 0.5/(vin_high - vin_offset);


   analog
      V(sigout) <+ gain*V(sigin) + 0.5*gain - gain*vin_offset;

endmodule