Liberate: Unable to characterize sequential cells for subthreshold operation

Hi there,

I am working with a 28nm PDK and want to characterize a D-FlipFlop and a D-Latch for voltages at 300mV and below.

Liberate is not able to calculate / estimate the constraints for the cells and throws this kind of errors:

ERROR (LIB-52): On arc 'DF_X1 CLK r D r setup_rising rise_constraint', the constraint search failed to find a solution within the search range. The cell will be marked as failed and the .lib will contain 'constraint_failed_value'.  To debug, save and review the simulation results using extsim_save_passed and extsim_save_failed. Possible causes include: constraint_delay_degrade too large; constraint_delay_degrade_abstol too large; constraint_search_bound too small. Modify the constraint parameters and rerun.
ERROR (LIB-52): On arc 'DF_X1 CLK r D f setup_rising fall_constraint', the constraint search failed to find a solution within the search range. The cell will be marked as failed and the .lib will contain 'constraint_failed_value'.  To debug, save and review the simulation results using extsim_save_passed and extsim_save_failed. Possible causes include: constraint_delay_degrade too large; constraint_delay_degrade_abstol too large; constraint_search_bound too small. Modify the constraint parameters and rerun.
ERROR (LIB-52): On arc 'DF_X1 CLK r D r hold_rising rise_constraint', the constraint search failed to find a solution within the search range. The cell will be marked as failed and the .lib will contain 'constraint_failed_value'.  To debug, save and review the simulation results using extsim_save_passed and extsim_save_failed. Possible causes include: constraint_delay_degrade too large; constraint_delay_degrade_abstol too large; constraint_search_bound too small. Modify the constraint parameters and rerun.
ERROR (LIB-52): On arc 'DF_X1 CLK r D f hold_rising fall_constraint', the constraint search failed to find a solution within the search range. The cell will be marked as failed and the .lib will contain 'constraint_failed_value'.  To debug, save and review the simulation results using extsim_save_passed and extsim_save_failed. Possible causes include: constraint_delay_degrade too large; constraint_delay_degrade_abstol too large; constraint_search_bound too small. Modify the constraint parameters and rerun.
ERROR (LIB-52): On arc 'DF_X1 CLK f falling_edge min_pulse_width_low', the constraint search failed to find a solution within the search range. The cell will be marked as failed and the .lib will contain 'constraint_failed_value'.  To debug, save and review the simulation results using extsim_save_passed and extsim_save_failed. Possible causes include: constraint_search_bound too small. Modify the constraint parameters and rerun.

I played with the parameters

constraint_search_bound 1e-6

constraint_search_bound_estimation_mode 3

But it did not work. Below you can find my char.tcl script and the corner.tcl file.I would be really happy about any hint from the more experienced liberat users.

Cheers,

Marten

char.tcl:

# Liberate control file
set rundir .
set cornerf [split  0.3_0.3_0_0_25 "_"]
lassign $cornerf vddVoltage vddsVoltage gndVoltage gndsVoltage temp
exec mkdir -p ${rundir}/ldb
exec mkdir -p ${rundir}/lib
exec mkdir -p ${rundir}/VITAL
exec mkdir -p ${rundir}/datasheet
source ${rundir}/corner.tcl
#set spicefiles /netlist/.scs
set_var extsim_model_include "$env(GIT_LIBDIR)/corners.scs"
#set_var extsim_deck_include 1
#set_var extsim_exclusive 0
#set_var sim_estimate_duration 0
#set_var sim_duration 1

set_var constraint_search_bound_estimation_mode 3
set_var constraint_search_bound 1e-6
set_var spectre_use_char_opt_license 1

#Save external sim files / log for failed cells. Options: none, deck, all, all_plus_em_reports
set_var extsim_save_failed all
#set_var extsim_leakage_option "accurate=1 brief=1 runlvl=6 method=gear gmindc=1e-15 gmin=1e-15 kcltest=1"
set_var extsim_option "accurate=1 brief=1 runlvl=6 autostop gmindc=1e-15 gmin=1e-15"
define_leafcell -extsim_model -type nmos -pin_position {0 1 2 3} {nfet}
define_leafcell -extsim_model -type pmos -pin_position {0 1 2 3} {pfet}
define_leafcell -extsim_model -type nmos -pin_position {0 1 2 3} {lvtnfet}
define_leafcell -extsim_model -type pmos -pin_position {0 1 2 3} {lvtpfet}
define_leafcell -extsim_model -type diode -pin_position {0 1} {diodenwx}
## When a combined cell subckt-file is used
foreach cell $cells {
    lappend spicefiles ${rundir}/NETLIST/${cell}.scs
}
#read_spice -format {spectre} $spicefiles
read_spice -format {hspice} liberate.spi
## Characterize the library for NLDM (default), CCS and ECSM timing.
char_library -ecsm -ccsn -ccsp -extsim Spectre -cells ${cells}
## Save characterization database for post-processing ##
write_ldb ${rundir}/ldb/CORE_${vddVoltage}_${vddsVoltage}_${gndVoltage}_${gndsVoltage}_${temp}.ldb
## Generate a .lib with ccs, ecsm LOCAL ###
write_library -overwrite -ecsm ${rundir}/lib/SUBVT28CORE_${vddVoltage}_${vddsVoltage}_${gndVoltage}_${gndsVoltage}_${temp}_ecsm.lib
write_library -overwrite -ccs  ${rundir}/lib/SUBVT28CORE_${vddVoltage}_${vddsVoltage}_${gndVoltage}_${gndsVoltage}_${temp}_ccs.lib
## Generate ascii datatsheet ###
write_datasheet -format text ${rundir}/datasheet/SUBVT28CORE

corner.tcl:

set cornerf [split 0.3_0.3_0_0_25 "_"]
lassign $cornerf vddVoltage vddsVoltage gndVoltage gndsVoltage temp
set_operating_condition -voltage $vddVoltage -temp $temp
set_vdd vdd! $vddVoltage
set_vdd vdd $vddVoltage
set_vdd vdds! $vddsVoltage
set_vdd vdds $vddsVoltage
set_gnd gnd! $gndVoltage
set_gnd gnd $gndVoltage
set_gnd gnds! $gndsVoltage
set_gnd gnds $gndsVoltage
set_var slew_lower_rise 0.3
set_var slew_upper_rise 0.7
set_var slew_lower_fall 0.3
set_var slew_upper_fall 0.7
set_var measure_slew_lower_rise 0.3
set_var measure_slew_upper_rise 0.7
set_var measure_slew_lower_fall 0.3
set_var measure_slew_upper_fall 0.7
#set_var max_transition 1.5e-06
set cells {  DL_X1 DF_X1 }

define_template -type delay -index_1        {150 300 450} -index_2        {0.0150 0.0500 0.1500} delay_template_3x3

define_template -type power -index_1        {150 300 450} -index_2        {0.0150 0.0500 0.1500} power_template_3x3

define_template -type constraint -index_1  {1001 1002 1003} -index_2  {1001 1002 1003} constraint_template_3x3

set inputs  {A B C D S}
set outputs {Z Q}
set clocks  {CLK}
set async  {STN RST}

define_cell -input $inputs  -output $outputs -clock $clocks -constraint  constraint_template_3x3 -delay       delay_template_3x3 -power       power_template_3x3 $cells