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What's the difference between gate level extraction and transistor level extraction in Calibre xRC tool.

Is there any fundamental difference between gate level extraction and transistor level extraction?

And in calibre xRC toolkit, what does C and CC represent for ?C means the parasitic to the substrate? and CC means the parasitic to the nets?

Best regards,

Mingliang

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Biasing over 9 years ago

Hi Andrew,

I am so sorry for the mistake. Maybe I should have a try to use Assura, then I can ask you more....

Thanks a lot for answer the "LOST" question....

Best regards,

Mingliang
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Biasing over 9 years ago

Hi Andrew,

I am so sorry for the mistake. Maybe I should have a try to use Assura, then I can ask you more....

Thanks a lot for answer the "LOST" question....

Best regards,

Mingliang
Cancel
Vote Up 0 Vote Down

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