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Assura LVS using: setenv OA_UNSUPPORTED_PLAT linux_rhel40_gcc44x

bartman

I am having an LVS problem and I noticed this post.  I am not sure if anyone is still around (based upon the 2010 responses) to reply.

At the end of the lvs report I have the following message:

Preprocessing layout network phase 2
*ERROR* Device 'pfet(Generic)' on Schematic is unbound to any Layout device.
*ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device.
*ERROR* UnBound devices found.
Info: All devices must be bound or filtered for comparison to be run.
Exiting nvn.

It implies that I have devices in the schematic which cannot be matched to a layout device.  I have tried this in calibre and succeeded in getting a clean LVS; so I know the layout and schematic do match.  I would like to have assura working as well.  One possible issue is in the use of multiplicity; m>1 for every transistor in the schematic.   The LVS checks using assura for devices which have m=1 have worked.  Is it possible to fix this problem ?

alan

Parents
  • bartman

    Hi Quek,


    I have made the changes; Assura claims to have failed the run.  The log file posted this error:

    SYNTAX ERROR found at line 1 column 23 of file *string*
    *Error* lineread/read: syntax error encountered in input
    ******* Non-recoverable error (no top-level or error handler)
    ******* Exiting program ...

    Although assura claims that it has failed to run; the directory containing the lvsdatabase (runname.lvsdb/ status, stat, etc.) seems to indicate that although assura abruptly terminated, the lvs checks were made and it did not pass.  The failure to pass remains the same.


    Two things worth noting: 1) this is a non-redhat OS; I have been able to run assura without a problem (that I was aware of) until recently.  So, I have modified assura/share/oa/bin/sysname in order to by-pass the OS issue.  I have no idea why it ran hundreds of times prior to just recently.  The second thing worth noting, 2) the dummy transistors are actual transistors placed in the schematic and appropriately wired (so they do not cause issues).  The layout transistors/devices is generated using: Connectivity->Generate->All From Source and when the layout is updated via the schematic using:  Connectivity->Update->Components and Nets.  Multiplicity, (m=2, 4 and 8) is used for many of the transistors in the schematic (and autogenerated in the layout); all previous designs had m=1 for every transistor & device. 

    I have succeeded in getting the lvs check to pass in calibre; so I am certain that it should be 'lvs clean'; however, I would like to get assura lvs to work properly.  Using XL I can identify ALL transistors in the schematic are in the layout.


    best regards,

    alan

Reply
  • bartman

    Hi Quek,


    I have made the changes; Assura claims to have failed the run.  The log file posted this error:

    SYNTAX ERROR found at line 1 column 23 of file *string*
    *Error* lineread/read: syntax error encountered in input
    ******* Non-recoverable error (no top-level or error handler)
    ******* Exiting program ...

    Although assura claims that it has failed to run; the directory containing the lvsdatabase (runname.lvsdb/ status, stat, etc.) seems to indicate that although assura abruptly terminated, the lvs checks were made and it did not pass.  The failure to pass remains the same.


    Two things worth noting: 1) this is a non-redhat OS; I have been able to run assura without a problem (that I was aware of) until recently.  So, I have modified assura/share/oa/bin/sysname in order to by-pass the OS issue.  I have no idea why it ran hundreds of times prior to just recently.  The second thing worth noting, 2) the dummy transistors are actual transistors placed in the schematic and appropriately wired (so they do not cause issues).  The layout transistors/devices is generated using: Connectivity->Generate->All From Source and when the layout is updated via the schematic using:  Connectivity->Update->Components and Nets.  Multiplicity, (m=2, 4 and 8) is used for many of the transistors in the schematic (and autogenerated in the layout); all previous designs had m=1 for every transistor & device. 

    I have succeeded in getting the lvs check to pass in calibre; so I am certain that it should be 'lvs clean'; however, I would like to get assura lvs to work properly.  Using XL I can identify ALL transistors in the schematic are in the layout.


    best regards,

    alan

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