Assura LVS using: setenv OA_UNSUPPORTED_PLAT linux_rhel40_gcc44x

Hi Alan

Would you please try the following?
a. In Assura LVS form, go to avCompareRules "General" section and set "abortOnUnboundDevices" as "nil". This will allows Assura LVS to always complete the run even if it thinks that there are unbound devices

b. In avCompareRules "Network" section, add "XZ" filterOptions. I suspect that the unbound schematic nfet and pfet are actually dummy devices.

c. Run Assura LVS


Best regards
Quek

Hi Quek,

I have made the changes; Assura claims to have failed the run.  The log file posted this error:

SYNTAX ERROR found at line 1 column 23 of file *string*
*Error* lineread/read: syntax error encountered in input
******* Non-recoverable error (no top-level or error handler)
******* Exiting program ...

Although assura claims that it has failed to run; the directory containing the lvsdatabase (runname.lvsdb/ status, stat, etc.) seems to indicate that although assura abruptly terminated, the lvs checks were made and it did not pass.  The failure to pass remains the same.

Two things worth noting: 1) this is a non-redhat OS; I have been able to run assura without a problem (that I was aware of) until recently.  So, I have modified assura/share/oa/bin/sysname in order to by-pass the OS issue.  I have no idea why it ran hundreds of times prior to just recently.  The second thing worth noting, 2) the dummy transistors are actual transistors placed in the schematic and appropriately wired (so they do not cause issues).  The layout transistors/devices is generated using: Connectivity->Generate->All From Source and when the layout is updated via the schematic using:  Connectivity->Update->Components and Nets.  Multiplicity, (m=2, 4 and 8) is used for many of the transistors in the schematic (and autogenerated in the layout); all previous designs had m=1 for every transistor & device. 

I have succeeded in getting the lvs check to pass in calibre; so I am certain that it should be 'lvs clean'; however, I would like to get assura lvs to work properly.  Using XL I can identify ALL transistors in the schematic are in the layout.

best regards,

alan

Hi Alan

Would you please check if the cmds have been added correctly (e.g. any typos, etc)? They should look like this:

avCompareRules(
   abortOnUnboundDevices(t)
   schematic( filterOptions("XZ") )
) ; avCompareRules


Best regards
Quek

Hi Quek,

I modified the compare rules via the assura menu; I paid special attention to what you had asked me to do and then realized that these rules were not 'activated'; once I activated them there was 'good news' & 'bad news'.

The good news (from the tail of the log file) is that it ran without aborting; although the LVS dialog box still does not activate:

Assura LVS terminated normally.

Run ended: Mon May 16 10:10:51 2016
*****  Assura terminated normally  *****

The bad news is that the layout and schematic, according to assura, still do not match.  As I mentioned before it passed with calibre; I looked at the file inside the run directory (e.g. run.lvsdb/stat) and here is what I have:

; Assura generated file -- DO NOT EDIT --
; Do NOT rely on the content of this file, it may change.
;
2 filter reduce swap match
1 3 ( ( "nfet" "nfet" "Generic" 0 0 0 0) ( "nfet_m0" "nfet_m0" "Generic" 8 8 0 0) ( "pfet" "pfet" "Generic" 0 0 0 0) ( "pfet_m0" "pfet_m0" "Generic" 9 9 0 0) ( "subc" "subc" "Generic" 1 1 0 0))

-----------
This is difficult to read because it is not easily matched to particular schematic devices.  I am having difficulty, especially with subc, to understand if assura is talking about a 'single' device or multiple devices.  All subc devices have m=1.  "nfet_m0", is there a way, for example, to tie this one back to a particular nfet in the schematic ?

best regards,

alan

Hi Alan

I totally agree with you that Assura should also give the same LVS match results as Calibre.

Would you please upload the .cls file (e.g. design.cls) in the run directory? This is the LVS report file.


Best regards
Quek

Hi Quek,

Unfortunately, I can see that there is a way to upload media; but not an ascii file.  So, I have copied it.

best regards,

alan

*******************************************************************************
****** ota_k2_tst1 schematic otaCells  <vs>  ota_k2_tst1 layout otaCells
*******************************************************************************
                                                                                                                                                                                                                            
Pre-expand Statistics                      
======================                          Original       
Cell/Device                               schematic  layout
(subc) Generic                                    5       1*
(nfet) Generic                                   12      48*
(pfet) Generic                                   14      88*
                                             ------  ------
Total                                            31     137

Filter Statistics
=================                               Original            Filtered
Cell/Device                               schematic  layout   schematic  layout
(nfet) Generic                                    0       0           0       0
(nfet_m0) Generic                                12      48*          8      40*
(pfet) Generic                                    0       0           0       0
(pfet_m0) Generic                                14      88*         10      80*
(subc) Generic                                    5       1*          5       1*

Reduce Statistics
=================                               Filtered             Reduced
Cell/Device                               schematic  layout   schematic  layout
(nfet) Generic                                    0       0           0       0
(nfet_m0) Generic                                 8      40*          8       8
(pfet) Generic                                    0       0           0       0
(pfet_m0) Generic                                10      80*          9       9
(subc) Generic                                    5       1*          1       1

Match Statistics
================                                  Total             Unmatched
Cell/Device                               schematic  layout   schematic  layout
(nfet) Generic                                    0       0           0       0
(nfet_m0) Generic                                 8       8           0       0
(pfet) Generic                                    0       0           0       0
(pfet_m0) Generic                                 9       9           0       0
(subc) Generic                                    1       1           0       0
                                             ------  ------      ------  ------
Total                                            18      18           0       0

Match Statistics for Nets                        20      20           0       0

=========================================================[ota_k2_tst1]
====== Parameter Mismatches for Instances =====================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 1)
Schematic Instance: D1  pfet_m0
Layout Instance:    avD15_57  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 2
"w" layout: 1.496e-05 schematic: 3.74e-06

Schematic Instance is the merged result of:  D1 D2
Layout Instance is the merged result of:  avD15_57 avD15_58 avD15_67 avD15_68
        avD15_69 avD15_70 avD15_79 avD15_80

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 2)
Schematic Instance: M1  pfet_m0
Layout Instance:    avD15_50  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 16 schematic: 2
"w" layout: 2.992e-05 schematic: 3.74e-06

Layout Instance is the merged result of:  avD15_50 avD15_52 avD15_53 avD15_55
        avD15_60 avD15_62 avD15_63 avD15_65 avD15_72 avD15_74 avD15_75 avD15_77
        avD15_82 avD15_84 avD15_85 avD15_87

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 3)
Schematic Instance: M2  pfet_m0
Layout Instance:    avD15_49  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 16 schematic: 2
"w" layout: 2.992e-05 schematic: 3.74e-06

Layout Instance is the merged result of:  avD15_49 avD15_51 avD15_54 avD15_56
        avD15_59 avD15_61 avD15_64 avD15_66 avD15_71 avD15_73 avD15_76 avD15_78
        avD15_81 avD15_83 avD15_86 avD15_88

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 4)
Schematic Instance: M16  pfet_m0
Layout Instance:    avD15_23  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 1
"w" layout: 1.496e-05 schematic: 1.87e-06

Layout Instance is the merged result of:  avD15_23 avD15_24 avD15_27 avD15_32
        avD15_33 avD15_36 avD15_43 avD15_44

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 5)
Schematic Instance: M15  pfet_m0
Layout Instance:    avD15_25  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 2
"w" layout: 1.496e-05 schematic: 3.74e-06

Layout Instance is the merged result of:  avD15_25 avD15_26 avD15_34 avD15_35
        avD15_45 avD15_46 avD15_47 avD15_48

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 6)
Schematic Instance: M13  pfet_m0
Layout Instance:    avD15_3  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 1
"w" layout: 7.48e-06 schematic: 1.87e-06

Layout Instance is the merged result of:  avD15_3 avD15_6 avD15_14 avD15_17

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 7)
Schematic Instance: M11  pfet_m0
Layout Instance:    avD15_4  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 2
"w" layout: 7.48e-06 schematic: 3.74e-06

Layout Instance is the merged result of:  avD15_4 avD15_5 avD15_15 avD15_16

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 8)
Schematic Instance: M14  pfet_m0
Layout Instance:    avD15_2  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 1
"w" layout: 1.496e-05 schematic: 1.87e-06

Layout Instance is the merged result of:  avD15_2 avD15_7 avD15_10 avD15_13
        avD15_18 avD15_21 avD15_30 avD15_39

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 9)
Schematic Instance: M12  pfet_m0
Layout Instance:    avD15_1  pfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 2
"w" layout: 1.496e-05 schematic: 3.74e-06

Layout Instance is the merged result of:  avD15_1 avD15_8 avD15_9 avD15_12
        avD15_19 avD15_20 avD15_31 avD15_40

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 10)
Schematic Instance: M3  nfet_m0
Layout Instance:    avD4_7  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 2
"w" layout: 3e-06 schematic: 1.5e-06

Layout Instance is the merged result of:  avD4_7 avD4_13 avD4_20 avD4_26

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 11)
Schematic Instance: M5  nfet_m0
Layout Instance:    avD4_1  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 1
"w" layout: 3e-06 schematic: 7.5e-07

Layout Instance is the merged result of:  avD4_1 avD4_12 avD4_14 avD4_25

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 12)
Schematic Instance: M4  nfet_m0
Layout Instance:    avD4_29  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 2
"w" layout: 3e-06 schematic: 1.5e-06

Layout Instance is the merged result of:  avD4_29 avD4_30 avD4_40 avD4_41

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 13)
Schematic Instance: M6  nfet_m0
Layout Instance:    avD4_28  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 1
"w" layout: 3e-06 schematic: 7.5e-07

Layout Instance is the merged result of:  avD4_28 avD4_31 avD4_39 avD4_42

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 14)
Schematic Instance: M7  nfet_m0
Layout Instance:    avD4_32  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 1
"w" layout: 3e-06 schematic: 7.5e-07

Layout Instance is the merged result of:  avD4_32 avD4_35 avD4_43 avD4_46

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 15)
Schematic Instance: M9  nfet_m0
Layout Instance:    avD4_33  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 4 schematic: 2
"w" layout: 3e-06 schematic: 1.5e-06

Layout Instance is the merged result of:  avD4_33 avD4_34 avD4_44 avD4_45

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 16)
Schematic Instance: M8  nfet_m0
Layout Instance:    avD4_2  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 1
"w" layout: 6e-06 schematic: 7.5e-07

Layout Instance is the merged result of:  avD4_2 avD4_5 avD4_8 avD4_11 avD4_15
        avD4_18 avD4_21 avD4_24

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(param 17)
Schematic Instance: M10  nfet_m0
Layout Instance:    avD4_3  nfet_m0

FETcomp has mismatched parameter(s):
"nf" layout: 8 schematic: 2
"w" layout: 6e-06 schematic: 1.5e-06

Layout Instance is the merged result of:  avD4_3 avD4_4 avD4_9 avD4_10 avD4_16
        avD4_17 avD4_22 avD4_23

=========================================================[ota_k2_tst1]
====== Summary of Errors ======================================================
===============================================================================

Schematic  Layout     Error Type
---------  ------     ----------
 17         17        Parameter Mismatches for Instances

Hi Alan

From the LVS report, it seems that Assura is reporting only parameter mismatch. Connectivity is ok. The parameter mismatch is caused by different nf and w values.

"nf" layout: 4 schematic: 1
"w" layout: 3e-06 schematic: 7.5e-07

This seems to be because of the way the schematic parameters are exported to the netlist. E.g. Calibre LVS uses "auCdl" CDF section. Assura uses "auLvs" CDF section. I am guessing that nf is not exported for auLvs and hence you are getting parameter mismatches for Assura LVS. You can check the exported schematic netlist as follows:

terminal> vldbToCdl design.sdb > design.sdb.cdl

The above cmd will convert the binary database design.sdb to an ascii file for viewing. You can then check if "nf" can be found in the netlist.


Best regards
Quek

Hi Quek,

I have run vldbToCdl and I do find nf in the netlist.  One peculiar thing regarding assura is that on the digital cells, around 100 or more, I have been able to pass lvs.  Some of the digital cells, buffers for example, did use nf > 1 and passed in all cases.  One parameter, m=1, for all of the digital cells (at least the ones I can think of).  I had questions about m=2, 4, 8; nfets used in device matching, as you know, might be placed in a way that causes lvs issues; for example, if you want the w of m2 to be 2X that of m1, then you might take both m1 & m2 with equal w's and arrange them:

m2;m1;m2 for better control of matching.  That has been done extensively.  It seems 'ok in calibre but it is difficult to tell with assura.  I have

I investigated this problem using the same ota with a different vendor pdk.  I had to use calibre to locate the lvs problem; once I fixed it I did run assura; assura crashed but the database file indicated that the schematic and layout match.  But, assura was still quite shaky.

best regards,

alan

Hi Alan

Maybe we should just focus on the parameter mismatch issue for now. From the LVS report, we can also tell that the final number of devices that are being compared is the same for both schematic and layout:

Match Statistics
================ Total Unmatched
Cell/Device schematic layout schematic layout
(nfet) Generic 0 0 0 0
(nfet_m0) Generic 8 8 0 0
(pfet) Generic 0 0 0 0
(pfet_m0) Generic 9 9 0 0
(subc) Generic 1 1 0 0
 ------ ------ ------ ------
Total 18 18 0 0

This means that the current parameter mismatch is not caused by the failure to expand schematic mFactored devices. My guess is that the rule deck is trying to compare totalNF and totalW but the CDF setup for auLvs is such that only finger NF and finger W are being exported. Hence this resulted in the parameter mismatch. You can examine the actual compare procedure in the compare rules file (e.g. compare.rul) to confirm this.

This is a test

By the way, you can upload a text file as follows:

a. Press the "Insert/Edit Media" button
b. In the "Media" form, change "Computer(Upload)" for the "From" field
c. Browse for a file on your computer

Here is an example:

This is a test