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  3. Create ideal buffer with verilogA

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Create ideal buffer with verilogA

BaaB
BaaB over 9 years ago

Hi,

With the help of Andrew last time relating to dependent sources, yesterday I tried a similar approach to create an ideal buffer.

I tried it and tested. Everything is OK. However, I have some questions relating to the code. Could you help me clarify it?

Here is the code I used to create an ideal buffer:

subckt ibuff (in out gnd)
V1 (out gnd) bsource v=v(in,gnd)
ends ibuff


It works as expected. But how input impedance of infinity and zero output impedance is realized from the code?

I see that the ideal buffer has infinite input impedance and zero output impedance too

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Simplest way would be to create the view in Virtuoso (File->New->CellView and then set the Type to "VerilogA"; paste in the code there). Then when you instantiate the symbol (it should prompt you to create a symbol when you exit the editor) in your schematic, it will automatically add the ahdl_include line in the netlist.

    You appear to have just specified the Verilog-A as a model file - you can't do that, because it's not in spectre syntax. It has to be included via an ahdl_include statement.

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Simplest way would be to create the view in Virtuoso (File->New->CellView and then set the Type to "VerilogA"; paste in the code there). Then when you instantiate the symbol (it should prompt you to create a symbol when you exit the editor) in your schematic, it will automatically add the ahdl_include line in the netlist.

    You appear to have just specified the Verilog-A as a model file - you can't do that, because it's not in spectre syntax. It has to be included via an ahdl_include statement.

    Regards,

    Andrew.

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