Create ideal buffer with verilogA

You could have just used a vcvs (voltage controlled voltage source) from analogLib to do this. Isn't it fairly obvious why this has infinite input impedance and zero output impedance? It is simply measuring the input voltage (it would draw no current) and then has an ideal voltage source at the output where the voltage just happens to be the measured input voltage - so there's no impedance included.

Put another way, I don't really understand why you are unsure as to why this would have ideal behaviour?

Regards,

Andrew.

Oh, and by the way, this is not Verilog A. A Verilog A model would look like this:

`include "disciplines.vams"
module ibuff(in, out, gnd);
electrical in, out, gnd;
input in;
output out;
inout gnd;

analog
  V(out,gnd) <+ V(in,gnd);

endmodule

Regards,

Andrew.

Thanks for the help. I was not sure how the input voltage is measured in simulator. But from what you said, it draws no current when measuring so it has infinite input impedance then.

I also thought about vcvs but I haven't tried that.

For the code, could you tell me how to include that code to make it work?

I tried the way as you said last time for dependent source but I got the following errors:

Loading /usr/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /usr/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /usr/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /usr/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /usr/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /home/huannguyen/simulation/ibuff_tb/spectre/schematic/netlist/input.scs
Reading file:  /usr/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /home/huannguyen/TSMC65/models/spectre/crn65gplus_2d5_lk_v1d0.scs
Reading file:  /home/huannguyen/TSMC65/models/spectre/mosCAPrf_ahdl.va
Reading link:  /usr/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /usr/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading link:  /usr/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /usr/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading file:  /home/huannguyen/TSMC65/models/spectre/mosCap_ahdl.va
Reading file:  /home/huannguyen/ibuff.scs

Error found by spectre during circuit read-in.
    ERROR (SFE-841): "/home/huannguyen/ibuff.scs" 1: Unexpected character ``' in netlist.
    ERROR (SFE-868): "/home/huannguyen/ibuff.scs" 1: Can not open input file `disciplines.vams'. No such file or directory. Ensure that the file exists and the path to the file is correct. Otherwise, use the -I<path> command-line option to specify the path to the file.
Warning from spectre during circuit read-in.
    WARNING (SFE-702): "/home/huannguyen/ibuff.scs" 2: Use of the comma character in node lists is not supported.
    WARNING (SFE-702): "/home/huannguyen/ibuff.scs" 2: Use of the comma character in node lists is not supported.
    WARNING (SFE-702): "/home/huannguyen/ibuff.scs" 3: Use of the comma character in node lists is not supported.
    WARNING (SFE-702): "/home/huannguyen/ibuff.scs" 3: Use of the comma character in node lists is not supported.
Error found by spectre during circuit read-in.
    ERROR (SFE-678): "/home/huannguyen/ibuff.scs" 8: Statement is not in Spectre format. Use `simulator lang=spice' to introduce spice language sections.
    ERROR (SFE-678): "/home/huannguyen/ibuff.scs" 11: Statement is not in Spectre format. Use `simulator lang=spice' to introduce spice language sections.

Simplest way would be to create the view in Virtuoso (File->New->CellView and then set the Type to "VerilogA"; paste in the code there). Then when you instantiate the symbol (it should prompt you to create a symbol when you exit the editor) in your schematic, it will automatically add the ahdl_include line in the netlist.

You appear to have just specified the Verilog-A as a model file - you can't do that, because it's not in spectre syntax. It has to be included via an ahdl_include statement.

Regards,

Andrew.

Thank you. You are right. I referred it in Model Libraries too. Now it works like a charm!