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Create ideal buffer with verilogA

Hi,

With the help of Andrew last time relating to dependent sources, yesterday I tried a similar approach to create an ideal buffer.

I tried it and tested. Everything is OK. However, I have some questions relating to the code. Could you help me clarify it?

Here is the code I used to create an ideal buffer:

subckt ibuff (in out gnd)
V1 (out gnd) bsource v=v(in,gnd)
ends ibuff

It works as expected. But how input impedance of infinity and zero output impedance is realized from the code?

I see that the ideal buffer has infinite input impedance and zero output impedance too

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BaaB over 9 years ago

Thank you. You are right. I referred it in Model Libraries too. Now it works like a charm!
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BaaB over 9 years ago

Thank you. You are right. I referred it in Model Libraries too. Now it works like a charm!
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