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  3. Is there a way to exclude parasitic capacitances of a MOS...

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Is there a way to exclude parasitic capacitances of a MOS in BSIM model?

BaaB
BaaB over 9 years ago

Is there a way to exclude parasitic capacitances of a MOS in BSIM model?

For example, I run TSMC18 with MOS BSIM3v3. How can I set all or some of parasitic capacitances such as Cgs, Cgd,... to zero?

Thank you.

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    The equations for these capacitances (which are really partial derivatives in bsim3v3 and bsim4) are complex and are affected by lots of parameters. I'm pretty certain there is no simple way to turn them off without (maybe) adjusting several parameters. In the case of the gate capacitances, a lot of that is going to be related to Cox which is determined from Tox - which is a pretty fundamental device parameter, and is likely to impact many other things. In bsim4 there's epsrox which is the relative dielectric constant (which multiplies the permittivity of free space) to form the capacitance. Maybe that could be set to 0 but I suspect that would break all sorts of other things too. Also, I don't see this parameter in bsim3v3.

    It strikes be as being completely pointless to turn this capacitance off - I've no idea what practical benefit that would have.

    So if you really want to do this, you'll have to wade through the bsim3v3 documentation (and maybe code from Berkeley) to figure out how to do this. Even then, I'm not convinced it can be done in isolation (i.e. not affecting anything else) because it's a totally non-physical thing to do, and that's not what device models are designed to do.

    Regards,

    Andrew.

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  • BaaB
    BaaB over 9 years ago

    Thank you, Andrew.

    There are some circuit problems that I guess relates to Cgd and some other capacitances. However, I don't know any other way to check if my guess is correct instead of turning these capacitances off.

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    I don't see customers in the real world trying to debug circuit problems by editing model parameters - usually those models are so complex, it's not feasible. Plus they are always wary of the risk of simulating with non-qualified models by mistake.

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