• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. inconsistency while measuring sub-threshold currents.

Stats

  • Locked Locked
  • Replies 5
  • Subscribers 125
  • Views 15684
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

inconsistency while measuring sub-threshold currents.

geovol
geovol over 9 years ago

Hi all,

I experience a strange issue when I simulate pmos and nmos devices operating in sub-threshold. The issue is as

follows:

I bias a pmos transistor of minimum channel length and width with ideal voltage sources: VG=VS=VDD, VB=VDD,

VD=0V. I perform a DC analysis and save the DC operating point. Surprisingly, when I annotate the DC operating

points, the ID of the transistor (which is biased in subthreshold) is lower than the DC current than is drawn from

the voltage sources connected at its Source and Drain terminals. The difference is significant, approximately an

order of magnitude or less depending on the bias conditions. This probably means that there is some extra leakage

current through the transistor which I am not able to see via the operating points. This issue is only present when

the transistor is biased in sub-threshold. In moderate and strong inversion, all currents are equal.



I have run this setup in several CMOS technologies, i.e. IBM 130nm, TSMC 0.35um, TSMC 90nm (all of them are

modeled with BSIM4.x). IC and Spectre versions are as follows:

IC 6.1.4-646.485 & IC 5.10.41_USR5.90.69 and Spectre 7.2.0 (64 bit).



Has anyone of you experienced a similar issue? Do you believe this inconsistency between current indications

might be due to modeling issues? Where does the extra leakage current come from, since both p-n junction diodes

are reverse-biased?



Thank you.

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    You're using a version of the simulator that is at least 6 years old. If there was a bug in bsim4, it's highly likely that it's been fixed by now if it is as apparent as you say. You say there's an order of magnitude difference, but don't see what sort of magnitude the currents are (if they're very small, there's a chance you're seeing numerical noise).

    Without specific details of the problem (ideally a test case that shows the problem) it's hard to comment further, so I suggest that if the problem still occurs once you've moved to a simulator version from this decade that you contact customer support providing the details of the problem (the circuit, simulation setup, and precise technology reference that you're using). There's also a potential problem with how the models have been implemented, although it seems unlikely that you'd see the same problem in multiple technologies if this is the reason.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • geovol
    geovol over 9 years ago

    Hi Andrew,

    Thanks for your reply.

    As you suggested I moved to MMSIM 13.1.1 64b (with IC 6.1.5 64b) and re-simulated my setup. The setup comprises of:

    A pmos transistor ("pfet33") from Global Foundries 130nm process ("cmrf8sf"), modeled with BSIM4.6, and biased as follows:

    VG=3.3V, VS=3.2V, VB=3.2V, VD=3.15V.

    Thus, the transistor operates in linear region (VSD=50mV) and deep sub-threshold (VSG=-0.1V). The strange issue that I described in my first post is still there, though less prominent.

    While the resistive drain current, id, equals -112.73fA, the total drain current, ide, equals -212.73fA, whereas the total source current, ise, equals 162.72fA.

    You can see these differences in the attached image.

    This issue is not present when the transistor becomes "on", e.g. VG is lowered to 2V. In this case, id=ide=ise.

    Do you think this inconsistency between same branch currents might be due to numerical noise?

    Actually, I need to calculate the "off" (sub-threshold) current  of a transistor connected to a circuit, which is biased in similar conditions. Apparently, I am not sure which of these currents corresponds to my "off" current. I suppose this should be id. Yet, I cannot understand the reason for such an inconsistency.  

    Best regards,

    George

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Given that all these currents are smaller than the usual tolerances (iabstol has a default of 1pA - and one of the convergence criteria is that the sum of the currents into each node should be less than reltol*current+iabstol), the currents actually look pretty accurate (with the exception of ids - but that's computed differently as an equation in the model, rather than being directly measured). I also don't know what you have gmin set to (it can't be the default, because that would lead to a 1e-12 conductance across the junction, which would give you a 3.2pA current across the junction (at least).

    I'd be surprised if the leakage currents in the models were that precisely modelled at this size of current, but if they are, then I think I'd need to see the precise simulator settings you're using before testing it myself to understand where the discrepancy comes from. It could be numerical simulator noise (although the currents through the sources add up, it may not be the current the device itself was expecting because it's below the tolerance).

    Perhaps you can post the complete input.scs you're using?

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • geovol
    geovol over 9 years ago

    Hi Andrew,

    Gmin is set to 1e-12 S. Therefore for Vbd=3.2V-3.15V=50mV, idb is equal to idb=1e-12A/V*50mV=50fA, not 3.2pA.  You can check this value in the attached picture above.

    Decreasing Gmin to 1e-15, all currents agree, i.e. |id|=|ide|=|ise|=112fA.

    Do you believe it is realistic to simulate my design for calculating leakage currents in the order of fA with Gmin=1e-15S ?

    Thank you,

    George.

    ps. input.scs file follows:

    // Generated for: spectre
    // Generated on: Jul 19 11:03:46 2016
    // Design library name: pmos
    // Design cell name: pmos
    // Design view name: schematic
    simulator lang=spectre
    global 0
    parameters vbp=3.2 vsp=3.2 vdp=3.15 vgp=3.3 l=400n m=1 nf=1 wf=500n
    include "/proj/cad/library/mosis/IBM_PDK/cmrf8sf/V1.8.0.4DM/Spectre/models/design.scs"
    include "/proj/cad/library/mosis/IBM_PDK/cmrf8sf/V1.8.0.4DM/Spectre/models/allModels.scs" section=tt
    include "/proj/txace/axa152131/gb130/saveop.scs"

    // Library name: pmos
    // Cell name: pmos
    // View name: schematic
    V16 (net023 0) vsource dc=vsp type=dc
    V12 (net027 0) vsource dc=vbp type=dc
    V11 (net030 0) vsource dc=vgp type=dc
    V10 (net022 0) vsource dc=vdp type=dc
    I7 (net022 net030 net023 net027) pfet33 l=l w=wf nf=nf m=1 par=1 ngcon=1 \
            ad=(wf*6e-07) as=(wf*6e-07) pd=(2*wf+2*6e-07) ps=(2*wf+2*6e-07) \
            nrd=2.2e-07/wf nrs=2.2e-07/wf rf_rsub=1 plnest=-1 plorient=-1 \
            pld200=-1 pwd100=-1 lstis=1 lnws=0 rgatemod=0 rbodymod=0 panw1=0p \
            panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p \
            panw9=0p panw10=0p sa=6e-07 sb=6e-07 sd=0u dtemp=0
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25.0 \
        tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
    dcOpInfo info what=oppoint where=rawfile
    dc dc param=vgp start=0 stop=3.3 step=0.01 oppoint=rawfile maxiters=150 \
        maxsteps=10000 annotate=status
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    save I7:s I7:d
    saveOptions options save=allpub

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Hi George,

    Apologies - didn't read the schematic carefully enough - of course you're right about the current.

    One should be a bit cautious about lowering gmin too much as this can lead to convergence difficulties (although with a single transistor that's unlikely to be a problem). You may also want to reduce iabstol too as you're below the convergence floor for current.

    As I said, how accurate the model is at this level I have no idea - you'd probably need to check with the foundry.

    Kind Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information