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inconsistency while measuring sub-threshold currents.

geovol

Hi all,

I experience a strange issue when I simulate pmos and nmos devices operating in sub-threshold. The issue is as

follows:

I bias a pmos transistor of minimum channel length and width with ideal voltage sources: VG=VS=VDD, VB=VDD,

VD=0V. I perform a DC analysis and save the DC operating point. Surprisingly, when I annotate the DC operating

points, the ID of the transistor (which is biased in subthreshold) is lower than the DC current than is drawn from

the voltage sources connected at its Source and Drain terminals. The difference is significant, approximately an

order of magnitude or less depending on the bias conditions. This probably means that there is some extra leakage

current through the transistor which I am not able to see via the operating points. This issue is only present when

the transistor is biased in sub-threshold. In moderate and strong inversion, all currents are equal.



I have run this setup in several CMOS technologies, i.e. IBM 130nm, TSMC 0.35um, TSMC 90nm (all of them are

modeled with BSIM4.x). IC and Spectre versions are as follows:

IC 6.1.4-646.485 & IC 5.10.41_USR5.90.69 and Spectre 7.2.0 (64 bit).



Has anyone of you experienced a similar issue? Do you believe this inconsistency between current indications

might be due to modeling issues? Where does the extra leakage current come from, since both p-n junction diodes

are reverse-biased?



Thank you.

Parents
  • geovol

    Hi Andrew,

    Thanks for your reply.

    As you suggested I moved to MMSIM 13.1.1 64b (with IC 6.1.5 64b) and re-simulated my setup. The setup comprises of:

    A pmos transistor ("pfet33") from Global Foundries 130nm process ("cmrf8sf"), modeled with BSIM4.6, and biased as follows:

    VG=3.3V, VS=3.2V, VB=3.2V, VD=3.15V.

    Thus, the transistor operates in linear region (VSD=50mV) and deep sub-threshold (VSG=-0.1V). The strange issue that I described in my first post is still there, though less prominent.

    While the resistive drain current, id, equals -112.73fA, the total drain current, ide, equals -212.73fA, whereas the total source current, ise, equals 162.72fA.

    You can see these differences in the attached image.

    This issue is not present when the transistor becomes "on", e.g. VG is lowered to 2V. In this case, id=ide=ise.

    Do you think this inconsistency between same branch currents might be due to numerical noise?

    Actually, I need to calculate the "off" (sub-threshold) current  of a transistor connected to a circuit, which is biased in similar conditions. Apparently, I am not sure which of these currents corresponds to my "off" current. I suppose this should be id. Yet, I cannot understand the reason for such an inconsistency.  

    Best regards,

    George

Reply
  • geovol

    Hi Andrew,

    Thanks for your reply.

    As you suggested I moved to MMSIM 13.1.1 64b (with IC 6.1.5 64b) and re-simulated my setup. The setup comprises of:

    A pmos transistor ("pfet33") from Global Foundries 130nm process ("cmrf8sf"), modeled with BSIM4.6, and biased as follows:

    VG=3.3V, VS=3.2V, VB=3.2V, VD=3.15V.

    Thus, the transistor operates in linear region (VSD=50mV) and deep sub-threshold (VSG=-0.1V). The strange issue that I described in my first post is still there, though less prominent.

    While the resistive drain current, id, equals -112.73fA, the total drain current, ide, equals -212.73fA, whereas the total source current, ise, equals 162.72fA.

    You can see these differences in the attached image.

    This issue is not present when the transistor becomes "on", e.g. VG is lowered to 2V. In this case, id=ide=ise.

    Do you think this inconsistency between same branch currents might be due to numerical noise?

    Actually, I need to calculate the "off" (sub-threshold) current  of a transistor connected to a circuit, which is biased in similar conditions. Apparently, I am not sure which of these currents corresponds to my "off" current. I suppose this should be id. Yet, I cannot understand the reason for such an inconsistency.  

    Best regards,

    George

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