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How to use PSS+PSTB or PSS+PAC to simulation the loop gain of the amplifier in the MDAC in each clock phases

Hello, everyone!

I am currently designing a amplifier for the multiplying dac (MDAC) for the pipeline ADC. The circuit diagram is show in Fig. 1. This circuit operates in two clock phases: phi1 and phi2. In phi1, the amplifier is auto-zeroing and its offset will be sampled in capacitor Cc. Vin is sampled in C1 and C2. In phi2, the amplifier will do the amplification. Clearly, the feedback factor of the amplifier in phi1 and phi2 is different. So I want to simulation the loop gain in phi1 and phi2 separately and also want to see the effect of different feedback factors.

Since this circuit is a discrete time circuit, it seems that I should use PSS analysis to find its operation point and do the small signal analysis to analysis the loop gain.

I also found a slide in the internet to teach how to use the PSS+PSTB simulation to analysis the loop gain of switched capacitor CMFB. The link is

lumerink.com/.../Loop%20Stability%20Analysis.pdf

However, I have a question about the method using in this slide. For better description, pls see Fig. 2 (actually page 28 of the slide). The SC CMFB also operates in two clock phases. The feedback capacitor of the CMFB circuit is different is each phase. So the question is how can the PSS analysis distinguish two clock phases and PSTB simulation results is corresponding to which clock phase?

So I want to make a clear statement of my question:

How to use PSS+PSTB or PSS+PAC to simulation the loop gain in each clock phase

Fig. 1

Fig. 2

Parents

ringamplifier over 9 years ago

Hello !

Andrew

This is the input.scs file

simulator lang=spectre
global 0
include "/home/yanrongshen/cdslocallib/artist/ahdlLib/quantity.spectre"
include "models.scs"
parameters a=25m Waz2=6 Waz1=6 Waz=8 Wout=2 Win=16 Wcm=2 Cload=.4p \
    cstable=0.8p Vcm=0.6 T=20n Vin=0m power=1.2 Cs=200f Cf=200f \
    pre=power/2.0

// Library name: ringamp2016
// Cell name: ringamp2nd
// View name: schematic
I13 (net060 net053 net054) nand_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I2 (net055 clk_master net057) nand_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I3 (clk_master clk_master net060) nor_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I12 (net055 net055 net494) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I11 (net069 net069 net055) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I10 (net054 net054 net069) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=250p trise=30p tfall=30p
I86 (net053 net053 net475) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I85 (net078 net078 net053) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I9 (net057 net057 net078) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=50p trise=30p tfall=30p
IPRB0 (net090 net277) iprobe
C16 (net359 net090) capacitor c=200.0f
C18 (net502 AGND) capacitor c=1.000f
C15 (net419 VCM) capacitor c=Cload
C13 (net411 net359) capacitor c=Cs
C14 (net359 net395) capacitor c=Cf
R6 (net502 AGND) resistor r=10M
W21 (VCM net359 Phase2e 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
W28 (net419 net375 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W24 (net457 net395 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W25 (net395 net502 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W27 (net457 net411 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W20 (net502 net419 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W23 (net277 net502 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W22 (net411 VCM Phase1 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
V3 (VCM AGND) vsource dc=600.0m type=dc
V0 (AGND 0) vsource type=dc
V1 (AVDD AGND) vsource dc=1.2 type=dc
V5 (DVDD 0) vsource type=dc
V15 (net375 0) vsource dc=pre type=dc
V16 (net457 VCM) vsource dc=Vin type=dc
I54 (net470 net486 net465) or_gate vlogic_high=1.2 vlogic_low=0 vtrans=0.6 \
        tdel=20p trise=20p tfall=20p
I53 (net486 net470 Phase2e) and_gate vlogic_high=1.2 vlogic_low=0 \
        vtrans=0.6 tdel=20p trise=20p tfall=20p
I2289 (net469 net470) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I57 (Phase2e inv_Phase2e) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2291 (net475 net469) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I2287 (net494 net483) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I58 (Phase2 inv_Phase2) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I55 (net465 net480) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I56 (net480 Phase2) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2292 (net483 Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I7 (net488 net486) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2293 (net470 net488) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2288 (Phase1 inv_Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
V4 (clk_master 0) vsource type=pulse val0=0 val1=1 period=T rise=30p \
        fall=30p width=T/2.0
G3 (net502 VCM net090 VCM) vccs gm=1m
simulatorOptions options reltol=1e-4 vabstol=1e-9 iabstol=1e-15 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=psf
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
pss pss fund=50M harms=0 errpreset=moderate tstab=500n
+    cmin=10a method=gear2only tstabmethod=gear2only maxacfreq=1G
+    annotate=status
pstb pstb start=1 stop=1G dec=100 probe=IPRB0 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
asserts info what=assert where=rawfile
saveOptions options save=allpub subcktprobelvl=2
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nand_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nor_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/or_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/and_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/not_gate/veriloga/veriloga.va"
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ringamplifier over 9 years ago

Hello !

Andrew

This is the input.scs file

simulator lang=spectre
global 0
include "/home/yanrongshen/cdslocallib/artist/ahdlLib/quantity.spectre"
include "models.scs"
parameters a=25m Waz2=6 Waz1=6 Waz=8 Wout=2 Win=16 Wcm=2 Cload=.4p \
    cstable=0.8p Vcm=0.6 T=20n Vin=0m power=1.2 Cs=200f Cf=200f \
    pre=power/2.0

// Library name: ringamp2016
// Cell name: ringamp2nd
// View name: schematic
I13 (net060 net053 net054) nand_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I2 (net055 clk_master net057) nand_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I3 (clk_master clk_master net060) nor_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I12 (net055 net055 net494) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I11 (net069 net069 net055) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I10 (net054 net054 net069) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=250p trise=30p tfall=30p
I86 (net053 net053 net475) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I85 (net078 net078 net053) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I9 (net057 net057 net078) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=50p trise=30p tfall=30p
IPRB0 (net090 net277) iprobe
C16 (net359 net090) capacitor c=200.0f
C18 (net502 AGND) capacitor c=1.000f
C15 (net419 VCM) capacitor c=Cload
C13 (net411 net359) capacitor c=Cs
C14 (net359 net395) capacitor c=Cf
R6 (net502 AGND) resistor r=10M
W21 (VCM net359 Phase2e 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
W28 (net419 net375 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W24 (net457 net395 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W25 (net395 net502 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W27 (net457 net411 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W20 (net502 net419 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W23 (net277 net502 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W22 (net411 VCM Phase1 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
V3 (VCM AGND) vsource dc=600.0m type=dc
V0 (AGND 0) vsource type=dc
V1 (AVDD AGND) vsource dc=1.2 type=dc
V5 (DVDD 0) vsource type=dc
V15 (net375 0) vsource dc=pre type=dc
V16 (net457 VCM) vsource dc=Vin type=dc
I54 (net470 net486 net465) or_gate vlogic_high=1.2 vlogic_low=0 vtrans=0.6 \
        tdel=20p trise=20p tfall=20p
I53 (net486 net470 Phase2e) and_gate vlogic_high=1.2 vlogic_low=0 \
        vtrans=0.6 tdel=20p trise=20p tfall=20p
I2289 (net469 net470) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I57 (Phase2e inv_Phase2e) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2291 (net475 net469) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I2287 (net494 net483) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I58 (Phase2 inv_Phase2) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I55 (net465 net480) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I56 (net480 Phase2) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2292 (net483 Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I7 (net488 net486) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2293 (net470 net488) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2288 (Phase1 inv_Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
V4 (clk_master 0) vsource type=pulse val0=0 val1=1 period=T rise=30p \
        fall=30p width=T/2.0
G3 (net502 VCM net090 VCM) vccs gm=1m
simulatorOptions options reltol=1e-4 vabstol=1e-9 iabstol=1e-15 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=psf
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
pss pss fund=50M harms=0 errpreset=moderate tstab=500n
+    cmin=10a method=gear2only tstabmethod=gear2only maxacfreq=1G
+    annotate=status
pstb pstb start=1 stop=1G dec=100 probe=IPRB0 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
asserts info what=assert where=rawfile
saveOptions options save=allpub subcktprobelvl=2
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nand_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nor_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/or_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/and_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/not_gate/veriloga/veriloga.va"
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