[Virtuoso] Weird issue with netlist generation

Hi there

I am trying to generate a system verilog netlist netilist and the netlister is istantiating a component with the wrong port order. Wrong meas tha port of a module m0 with portlist (a,b,c) is connected as m0 i_im0(x,y,z) while I would have expected (expectations come from the schematic) m0 i_m0(y,z,x) (I am trying to make things simple, hope this is clear)

Question is: where the netlister get the information on ow to associate the port order to the higher level nets?

As s side comment I was always be unpleased about the positionalport assignment from this kind of tolls: explicit assignment would have been better, at the expense of a little bit more dis=k space ...)

Thanks muc