Cadence layout suite XL - some overlap regions get highlighted in yellow

Hi,

if there is a marker, XL thinks there is something wrong. Please open the Annotation Browser Assistant and you should find the entry for the marker there with an explanation what XL has to complain about your layout. Since XL is connectivity aware, this might be a wrong connection (short).

Marc

Hi Marc.

Thanks for your quick reply!

I indeed find that the yellow highlighted regions have correspondence with the entries in the Annotation Browser Assistant under the "Shorts" section.

One question: Although Virtuoso is detecting these, but that doesn't mean that the shorts are unintended; so, is there a way to disable this highlighting?

( I tried to click on the eye-shaped icon (Set highlight state) in Annotation Browser, but that doesn't seem to work in this regard)

Regards.

Hi,

the question is is, why would you like to have a short in your layout? XL is comparing schematic connectivity with the layout connectivity. If you think you need to have that connection in the layout you should also have it in the schematic or your LVS check will complain later. If the device in question is a dummy device, you can tell XL to ignore that device ( right click on the instance name in the navigator and "Add Ignore"), or you add it to the schematic and make it a legal connection.
Ofcourse you can switch of the whole connectivity check in the XL options, but then it would not make any sense to use Layout XL at all.

Regards,
Marc

Hi Marc,

I understand what you mean to say, but, strangely, I am finding that some regions of overlapping drawn shapes of the same layer (like say, metal-1) meant to comprise a single net is showing some highlighting!

Like in the screenshot below, you can see that some portions of overlapping metal-1 are getting highlighted in yellow (although the whole metal-1 here is part of the same net "vss") - also, the layout itself is LVS clean.

I am not able to grasp what's the mistake! Would you please point out if any?

Thanks.

Hi,

what is the message in the Annotaion Browser? Also select one of the instances and check the pin connectivity in the Property Editor Assistant.
I can give you only pointers here. Without knowing the pdk and design it pretty hard to tell exactly whats going wrong.
A LVS clean design is not necessarily XL clean. You can manually draw a transistor with a bunch of polygons and your LVS might be happy about it,
while XL is not able to identify any device out of this stack of shapes.

Regards,
Marc

Hi Marc,

I understand that it's hard to debug without having full information.

I am providing two screenshots of the Annotation Browser messages, with zoomed version of corresponding layout region (showing the highlighted region).

This is layout of an analog circuit, having common centroid fingers; I think that Virtuoso is somehow not able to correlate which finger corresponds to which MOS, with respect to the schematic.

This is evident from Property editor assistant - it is showing different net names for overlapping same layers (meant to be the same net) - hence the apparent "short":

(FYI, I am using Calibre for LVS.)

Can these warnings of shorts highlighted by Virtuoso be neglected here?

Hi,

I guess your device binding is wrong. You probably have 2 or more schematic MOS with several fingers each and now on the layout side you implemented them wrong from connectivity viewpoint. Electrically it is OK but XL can't figure that out. Lets say you have MOS M1 and M2, 2 fingers each. That gives you 4 devices on the layout side M1.1 M1.2 M2.1 M2.2. You want your layout look like this:

M1.1 M2.1
M2.2 M1.2

But you implemented it like this:

M1.1 M1.2
M2.1 M2.2

and wired it "wrong". Like I said, electrically OK and the LVS can take it, but XL can't. This is a "mistake" many people make, since it is the easiest way to do it.

You can delete the markers directly in the Annotation Browser, but they will reappear as soon as you extract the connectivity again.

Regards,
Marc

Thank you Marc for all of your answers :) they were helpful.
Please have my regards.