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probe different point on power nets in av_extracted view

primemath

Hi,
In my design there are multiple hierarchy and i have done the av_extraction at the top level now i want to power net at the lowest level but i am not able to do so can you pls guide me on how to do so.
I am using  virtuoso 6.1.6-64b for av_extraction and ultrasim 2016 for simulations.
Regards,
Priyankar

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  • primemath
    Andrew,
    I have done the av_extraction of my chip now when i am simulating it using ultrasim and trying to probe that vdd net (**:VDD) connected to transistor source i am observing it as an ideal supply (no droop) observed. So i wanted to know what is the right way to do the "power net" extraction and how to probe the power net close to the source of the transistor.

    Regards,
    Priyankar
Reply
  • primemath
    Andrew,
    I have done the av_extraction of my chip now when i am simulating it using ultrasim and trying to probe that vdd net (**:VDD) connected to transistor source i am observing it as an ideal supply (no droop) observed. So i wanted to know what is the right way to do the "power net" extraction and how to probe the power net close to the source of the transistor.

    Regards,
    Priyankar
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