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Requesting any reference to intelligent LVS issue debugging

saikatc

Hi,

I am working on analog circuit design using Cadence Virtuoso. The layout Suite I use is version IC6.1.6-64b.500.8

I never had any formal training on layout design. In last two years, I gathered only hands on knowledge by experimenting a lot. However, in last few months I am struggling with LVS issues which I am still unable to solve. I am requesting for any intelligent reference where I can get some help regarding the same.

Regards,

Saikat Chatterjee

  • VadimBorisov

    Hi,

    give us more information please. Because it isn't clear what do you mean.

    Which tool are you using for LVS verification? 

  • saikatc
    Hi,

    I am designing the schematic and layout using Cadence Virtuoso version IC6.1.6-64b.500.8
    For debugging the LVS errors, I am manually doing it using circuit theory. Nothing else.
  • VadimBorisov
    what exactly is the issue?
    Please add some examples of your problems.
  • saikatc

    The current issue where I found myself clueless, is I am having connectivity problems. Though I checked the connectivity manually, but it doesn't resolve the problem in layout. There are two distinct connectivity problems.

    1. The bulk is shorted with the source in case of PMOS. However in layout, it is not recognised. The layout still recognises them differently. The circuit has a low voltage part and a high voltage part. For the low voltage MOS I have VDD and VDDS. Whereas, for the high voltage part there is VDD1. VDD and VDD1 are connected to the corresponding PMOS and VDDS is connected to the bulk of low voltage PMOS. However, PMOS in the higher voltage side in the layout is searching for vdds. 

    2. In layoutXL, one can check the connectivity in the layout corresponding to the schematics if a schematic driven layout is drawn. Since I drew the layout completely manually, even if I try to open it in LayoutXl; it doesn't help me to check the connectivity. Perhaps it would be nicer to have something like that.

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