Stats

  • Locked Locked
  • Replies 4
  • Subscribers 126
  • Views 13798
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Requesting any reference to intelligent LVS issue debugging

saikatc

Hi,

I am working on analog circuit design using Cadence Virtuoso. The layout Suite I use is version IC6.1.6-64b.500.8

I never had any formal training on layout design. In last two years, I gathered only hands on knowledge by experimenting a lot. However, in last few months I am struggling with LVS issues which I am still unable to solve. I am requesting for any intelligent reference where I can get some help regarding the same.

Regards,

Saikat Chatterjee

Parents
  • VadimBorisov

    Hi,

    give us more information please. Because it isn't clear what do you mean.

    Which tool are you using for LVS verification? 

Reply
  • VadimBorisov

    Hi,

    give us more information please. Because it isn't clear what do you mean.

    Which tool are you using for LVS verification? 

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.