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Problem with simulating a PVS ERC spice netlist in spectre plus a skill for spice netlist reduction

RaghavasimhanT

Hello forums,

1) I have an age old problem that I know not how to resolve. I have a layout and I created the spice netlist from it using PVS ERC. I cleaned up the resulting netlist (by removing the coordinates $X and $Y) and I added it to a library. I created the auCdl and spectre views and added the required commands in the .simrc file. Then I tried simulating the cell, but I get the error that the "Instance M0 has no valid master". It happens for all transistors in the spice netlist. I do not know how to fix it. I can do spiceIn, create the schematic and then use it to simulate, but I wish to simulate the spice in spectre instead of going through that longwinded route. Could someone please tell me what I am doing wrong? For the sake of information, this is my spice netlist and the library description:

*******************************************
* Sub cell: xx
*******************************************
.subckt xx I ZN power ground
** N=5 EP=4 FDC=12
M0 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M1 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M2 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M3 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M4 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M5 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M6 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M7 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M8 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M9 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M10 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M11 power I ZN power pch_hvt L=6e-08 W=5.2e-07
.ends xx

//-------------------------------------------------------------
//Typical case (typical parasitics values)
//-------------------------------------------------------------
section CDL_TYP
simulator lang=spice insensitive=yes
.include "./csl_all.inc"
.include "./csl_hvt_all.inc"
.include "./csl_lvt_all.inc"
simulator lang=spectre insensitive=yes
endsection CDL_TYP

2) When I generate the netlist using PVS ERC, it gives the individual transistors based on their location. Is there any way (skill function) so that the mosfets can be smashed and I can get a netlist which includes the principal transistors with the number of fingers rather than each finger listed as an individual transistor?

Thanks a lot in advance,

Raghavan

  • RaghavasimhanT

    P.S: I am using virtuoso 6.1.7 and ADE Explorer and in my environment options I do not see "Use subcircuit as topcircuit" option. Can anyone guide me as to where is it located?

  • Andrew Beckett

    This is a fairly unusual way of generating a netlist from PVS; the usual way would be to use QRC to generate an extracted view (even if it was an LVS extracted view without parasitics) as that will join everything up so that it's netlistable.

    If you're just adding a spectre text view, you will need to use a recent IC617 subversion (may even need to be IC617 ISR9) as netlisting support for these views has only recently been added.

    If you need to know about collapsing parallel transistors in the PVS ERC output, that is a question I can't answer (without doing a bunch of research as I don't know PVS inside out - I'm a bit busy currently). So you'd need to contact customer support.

    For your last question (in the PS), this shows up for me. Check the MMSIM version  you're using; it must be at least MMSIM12.1.1 (earlier spectre versions didn't support this and the UI checks to ensure that you're using a suitable version that supports this; also make sure you don't have $SPECTRE_FEATURE_FILE set - or at least if you do (maybe you're using a wrapper around spectre), it points to the spectre.dat in the MMSIM version  you're using.

    Regards,

    Andrew.

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