Problem with simulating a PVS ERC spice netlist in spectre plus a skill for spice netlist reduction

Hello forums,

1) I have an age old problem that I know not how to resolve. I have a layout and I created the spice netlist from it using PVS ERC. I cleaned up the resulting netlist (by removing the coordinates $X and $Y) and I added it to a library. I created the auCdl and spectre views and added the required commands in the .simrc file. Then I tried simulating the cell, but I get the error that the "Instance M0 has no valid master". It happens for all transistors in the spice netlist. I do not know how to fix it. I can do spiceIn, create the schematic and then use it to simulate, but I wish to simulate the spice in spectre instead of going through that longwinded route. Could someone please tell me what I am doing wrong? For the sake of information, this is my spice netlist and the library description:

*******************************************
* Sub cell: xx
*******************************************
.subckt xx I ZN power ground
** N=5 EP=4 FDC=12
M0 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M1 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M2 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M3 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M4 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M5 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M6 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M7 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M8 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M9 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M10 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M11 power I ZN power pch_hvt L=6e-08 W=5.2e-07
.ends xx

//-------------------------------------------------------------
//Typical case (typical parasitics values)
//-------------------------------------------------------------
section CDL_TYP
simulator lang=spice insensitive=yes
.include "./csl_all.inc"
.include "./csl_hvt_all.inc"
.include "./csl_lvt_all.inc"
simulator lang=spectre insensitive=yes
endsection CDL_TYP

2) When I generate the netlist using PVS ERC, it gives the individual transistors based on their location. Is there any way (skill function) so that the mosfets can be smashed and I can get a netlist which includes the principal transistors with the number of fingers rather than each finger listed as an individual transistor?

Thanks a lot in advance,

Raghavan