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Extracted simulation not working properly - netlist problem...?

cescoz

Hello everyone,

PROBLEM EXPLANATION

I am facing a strange problem. First of all, I am using ICFB (a very old version).

I have a very simple cell made of 4 transistor. This cell has a schematic view, a layout and an extracted view.

I can do simulations with the schematic view (everything work as expected) using ADE and Spice. Then, the DRC and LVS on the layout give no error. 

At this point, I want to run the exact same simulation on the extracted view.

In order to do so, I go to Setup->Environment and in the Switch View List I insert "extracted" as the first element.

I then run the simulation and the result is the _exact opposite waveform_ at the output. (the block is supposed to act as a "digital" block, so I really mean that where I expect to see a "1" I get "0" and viceversa).

Now, if I check the netlists that are produced after the schematic and extracted simulations (in ADE, I go to Simulation -> Netlist -> Display Final) they don't exactly match:

====== Schematic Netlist ======
M4 NET4 B 0 0  NCH  
M3 Y A NET4 0  NCH  
M1 Y B NET15 VDD!  PCH
M0 NET15 A VDD! VDD!  PCH 
======= Extracted netlist ========
M3 Y B 2 4  PCH  
M5 4 A 2 4  PCH 
M6 8 B 1 8  NCH 
M9 Y A 1 8  NCH 
NB: I omitted information about device size because those info are correct.
===========================
As you may notice, in the extracted netlist the GND! and VDD! connection are not recognized correctly.
The devices have the correct number of terminals connected to the same node (node "4" for the PCH, and node "8" for the NCH) BUT they are not explicitly connected to VDD! and GND! respectively. Notice, however, that the signal levels I see in the simulation are correct (between 0 and 2.5 V).
FIRST PROPOSED SOLUTION
 

A colleague suggested that I add manually pins on the layout; the point is that the pins are there both in the layout and in the extracted view. With this, I mean that if I open the extracted view, I can select the net, and the net is correctly connected to VDD! (same goes for gnd!)
SECOND PROPOSED SOLUTION
 

Searching on google, I found someone suggesting that I put explicitly the VDD and GND pins in my symbol, so that I can connect them explicitly. I might try this, but this is not an acceptable solution for me because it would mean a redesign of a huge amount of cells. Plus, it is an already existing design, so all these simulations were done before.
Any idea where I might look into to find a solution?
Thanks a lot for any help!
Francesco

Parents
  • Andrew Beckett

    Hi Francesco,

    Can you contact customer support? If you're from a University, maybe you can contact whoever your support channel is (e.g. if you're at a European University, then it would be Europractice, probably).

    It's going to be hard to figure out without seeing the data - there's just too many variables - it depends on how the rules are set up, it depends on how exactly it's failing. Debugging via screenshots in a forum works sometimes, but it's going to be difficult (and time consuming).

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    Hi Francesco,

    Can you contact customer support? If you're from a University, maybe you can contact whoever your support channel is (e.g. if you're at a European University, then it would be Europractice, probably).

    It's going to be hard to figure out without seeing the data - there's just too many variables - it depends on how the rules are set up, it depends on how exactly it's failing. Debugging via screenshots in a forum works sometimes, but it's going to be difficult (and time consuming).

    Regards,

    Andrew.

Children
No Data

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