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import physical verilog netlist in Virtuoso

oAwad

I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command:

-phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple supply voltages.

-includePowerGround:    Includes power and ground connections in the netlist file.

-includePhysicalInst:   Includes physical instances, such as fillers.

WhenI try to import this netlist in Virtuoso, I get these warnings for all std cells:


WARNING (VERILOGIN-111): Cannot connect the terminal VDD in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-111): Cannot connect the terminal VSS in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-551): Number of pins on symbol DFF_X2 in library NangateOpenCellLibrary differ from the number of ports in
the HDL module description.

When I open the symbol of DFF_X2, there is no VDD and VSS symbol, so should I update the symbol of all std cells manually to have the VDD and VSS symbols ?

(I can find "VDD!" and "VSS!" pins in DFF_X2 schematic but not in its symbol)

Additionally, I get these warnings for FILLER cells:

WARNING (VERILOGIN-72): Could not find the symbol master for the instance FILLER_5. Therefore the functional
view will not have this instance.

And again there is no symbol view for FILLER cells in the std cell library.

Since, all std cells schematics have VDD! and VSS! pins but their symbols don't, was this made so that Virtuoso power these pins virtually without an explicit power source and ground ? or this is wrong and I have to update all symbols manually ?

Finally, power and ground are called "VDD" and "VSS" respectively in my verilog netlist, however they are written as "VDD!" and "VSS!" in all std cells schematics. So what is the difference between "VDD" and "VDD!" ?

Thanks

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  • Andrew Beckett

    OK, first thing to consider is whether you actually have multiple powers and grounds. This symbol library (from the look I've had at it) isn't designed to support multiple powers and grounds; each schematic has a global power and ground called VDD! and VSS! (in Virtuoso, global signals are typically suffixed with an exclamation mark). That means that all the powers and grounds in the standard cells themselves do not have distinct connections. There are pins (with global names) on the schematic, but not on the symbols.

    If you don't have multiple powers and grounds on the physical implementation side, don't use the -includePowerGround. Maybe you don't need -phys wither.

    If you don't have symbols for the filler cells, I suggest you omit the -includePhysicalInst.

    If you do have multiple powers and grounds in the design, the best way to achieve this is to edit the schematics for the standard cells. You'll need to do this for all of them (bear in mind they weren't designed for this use model, so it's a bit of work - although not too painful).

    1. Edit the VDD! pin and change the name to VDD. You'll find probably there's a small (blue) text label next to the pin that also renames from VDD! to VDD. Remove this label.
    2. Do the same for VSS! - change that to VSS and remove the VSS label.
    3. Use Create->Net Expression and fill in the property as VDD and default value as VDD!. Then click on the VDD pin
    4. Do the same for the VSS pin (property VSS, default value VSS! and click on the VSS pin)
    5. Check and save the schematic

    Now, when you do an Import Verilog (I don't know which version you're using - this is for IC617), go to the Schematic Generation Options tab and expand the "Reference Schematic View for Inherited Connections". In the List of Views field that appears, enter "schematic". In IC616 it's on the same tab, but is called Reference Schematic Views and is about three-quarters of the way down the form.

    Then what will happen is that when you import the Verilog, it will see that the instance in the Verilog has VDD and VSS pins, and it will then look for these pins in the reference schematic view and instead of connecting up a pin, it will add a netSet property on the instance to connect the power connections using inherited connections.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    OK, first thing to consider is whether you actually have multiple powers and grounds. This symbol library (from the look I've had at it) isn't designed to support multiple powers and grounds; each schematic has a global power and ground called VDD! and VSS! (in Virtuoso, global signals are typically suffixed with an exclamation mark). That means that all the powers and grounds in the standard cells themselves do not have distinct connections. There are pins (with global names) on the schematic, but not on the symbols.

    If you don't have multiple powers and grounds on the physical implementation side, don't use the -includePowerGround. Maybe you don't need -phys wither.

    If you don't have symbols for the filler cells, I suggest you omit the -includePhysicalInst.

    If you do have multiple powers and grounds in the design, the best way to achieve this is to edit the schematics for the standard cells. You'll need to do this for all of them (bear in mind they weren't designed for this use model, so it's a bit of work - although not too painful).

    1. Edit the VDD! pin and change the name to VDD. You'll find probably there's a small (blue) text label next to the pin that also renames from VDD! to VDD. Remove this label.
    2. Do the same for VSS! - change that to VSS and remove the VSS label.
    3. Use Create->Net Expression and fill in the property as VDD and default value as VDD!. Then click on the VDD pin
    4. Do the same for the VSS pin (property VSS, default value VSS! and click on the VSS pin)
    5. Check and save the schematic

    Now, when you do an Import Verilog (I don't know which version you're using - this is for IC617), go to the Schematic Generation Options tab and expand the "Reference Schematic View for Inherited Connections". In the List of Views field that appears, enter "schematic". In IC616 it's on the same tab, but is called Reference Schematic Views and is about three-quarters of the way down the form.

    Then what will happen is that when you import the Verilog, it will see that the instance in the Verilog has VDD and VSS pins, and it will then look for these pins in the reference schematic view and instead of connecting up a pin, it will add a netSet property on the instance to connect the power connections using inherited connections.

    Regards,

    Andrew.

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