import physical verilog netlist in Virtuoso

OK, first thing to consider is whether you actually have multiple powers and grounds. This symbol library (from the look I've had at it) isn't designed to support multiple powers and grounds; each schematic has a global power and ground called VDD! and VSS! (in Virtuoso, global signals are typically suffixed with an exclamation mark). That means that all the powers and grounds in the standard cells themselves do not have distinct connections. There are pins (with global names) on the schematic, but not on the symbols.

If you don't have multiple powers and grounds on the physical implementation side, don't use the -includePowerGround. Maybe you don't need -phys wither.

If you don't have symbols for the filler cells, I suggest you omit the -includePhysicalInst.

If you do have multiple powers and grounds in the design, the best way to achieve this is to edit the schematics for the standard cells. You'll need to do this for all of them (bear in mind they weren't designed for this use model, so it's a bit of work - although not too painful).

1. Edit the VDD! pin and change the name to VDD. You'll find probably there's a small (blue) text label next to the pin that also renames from VDD! to VDD. Remove this label.
2. Do the same for VSS! - change that to VSS and remove the VSS label.
3. Use Create->Net Expression and fill in the property as VDD and default value as VDD!. Then click on the VDD pin
4. Do the same for the VSS pin (property VSS, default value VSS! and click on the VSS pin)
5. Check and save the schematic

Now, when you do an Import Verilog (I don't know which version you're using - this is for IC617), go to the Schematic Generation Options tab and expand the "Reference Schematic View for Inherited Connections". In the List of Views field that appears, enter "schematic". In IC616 it's on the same tab, but is called Reference Schematic Views and is about three-quarters of the way down the form.

Then what will happen is that when you import the Verilog, it will see that the instance in the Verilog has VDD and VSS pins, and it will then look for these pins in the reference schematic view and instead of connecting up a pin, it will add a netSet property on the instance to connect the power connections using inherited connections.

Regards,

Andrew.

Hello Andrew,

Thank you for your reply. I can't find any VDD or VSS in the exported verliog netlist without any attributes ("saveNetlist design.v"), so I don't know if this will be ok in verilog import in Virtuoso.

I'm using IC614 (sorry for being outdated). Here is my .ihdlParamFile:

DirLabel =/root/Desktop/AES128bits/encounter

Target Library = NangateOpenCellLibrary

Reference Libraries =NangateOpenCellLibrary

Verilog Design Files = design.v

-y Options =

Library Extn. =

-v Options =

-f Options =

Ignore Modules File =

Import Modules File =

Log File =./verilogIn.log

Work Area =/tmp

Power Net =VDD!

Ground Net =VSS!

Global Signals =

Net Expression Property Name for Power Net =vdd

Net Expression Property Name for Ground Net =gnd

Create Net Expression =false

Connect By Name Nets =

Import Modules That Match Existing Target Library Cells =false

Verilog Cell Modules =Create Symbol Only

Verilog Structural Modules View =schematic

Functional View Name =functional

Netlist View Name =netlist

Schematic View Name =schematic

Symbol View Name =symbol

Name Map Table = ./verilogIn.map.table

Sheet Size =none

Pin Placement Flag =Left and Right Sides

Pin Placement File =

Label Size =0.062500

Maximum Number Of Rows =1024

Maximum Number of Columns =1024

Line-Line Spacing =   0.20000

Line-Component Spacing =   0.50000

Density Level =0

Full Place and Route =true

Fast labels =false

Minimize Cross Over =false

Generate Square Schematics =true

Extract Schematics =true

Ignore Extra Pins =false

No Dummy Nets In Netlist View =false

Verbose =false

Generate Snap Space Properties =true

Through CellView Library =basic

Through CellView Cell =cds_thru

Through CellView View =symbol

Continuous Assignment CellView Library =basic

Continuous Assignment CellView Cell =patch

Continuous Assignment CellView View =symbol

Pre Compiled Library =

Destination IR Lib =

ViewName for IR Library =hdl

Only Compile a Verilog Library =false

Can you tell me what to change ?

Do you need to change anything? There's generally no need to have power in the verilog if there's only one set of supplies. The supply connections are defined as globals within the standard cells; there's no need for them to be mentioned in the Verilog in that case (in general digital designers are concerned about the signal flow, not the supplies). 

The symbols don't have supplies on them in the library, so nothing needs to be connected up.

It's unclear to me if anything isn't working for you if you import the Verilog which doesn't contain power/ground information. I'd expect that to work... if it doesn't, you'd need to explain what doesn't work.

Andrew.

Hello Andrew,

I imported the verilog netlist with no attributes ("saveNetlist design.v") with no errors. But when I perform Calibre LVS check, I get errors for every cell stating that the cell in layout have power and ground ports while that in schematic don't.

Error: Different numbers of ports (see below).
Error: Power net missing in source. Ground net missing in source.

I want to run LVS in order to run Calibre PEX after wards to get the SPICE netlist and do post-layout simulations.

Should I edit all std cells in the library to have power and ground pins in their symbols and them import the verilog netlist using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst" ?

I very much doubt that you need to edit the standard cells to add these pins to each symbol (and schematic). Having standard cells without power pins is pretty common.

This is really far beyond what can reasonably be supported in a community forum (especially as you're asking about LVS with a non-Cadence tool that I don't have access to). Do you have a supervisor at your University that can help?

Andrew.