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import physical verilog netlist in Virtuoso

oAwad

I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command:

-phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple supply voltages.

-includePowerGround:    Includes power and ground connections in the netlist file.

-includePhysicalInst:   Includes physical instances, such as fillers.

WhenI try to import this netlist in Virtuoso, I get these warnings for all std cells:


WARNING (VERILOGIN-111): Cannot connect the terminal VDD in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-111): Cannot connect the terminal VSS in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-551): Number of pins on symbol DFF_X2 in library NangateOpenCellLibrary differ from the number of ports in
the HDL module description.

When I open the symbol of DFF_X2, there is no VDD and VSS symbol, so should I update the symbol of all std cells manually to have the VDD and VSS symbols ?

(I can find "VDD!" and "VSS!" pins in DFF_X2 schematic but not in its symbol)

Additionally, I get these warnings for FILLER cells:

WARNING (VERILOGIN-72): Could not find the symbol master for the instance FILLER_5. Therefore the functional
view will not have this instance.

And again there is no symbol view for FILLER cells in the std cell library.

Since, all std cells schematics have VDD! and VSS! pins but their symbols don't, was this made so that Virtuoso power these pins virtually without an explicit power source and ground ? or this is wrong and I have to update all symbols manually ?

Finally, power and ground are called "VDD" and "VSS" respectively in my verilog netlist, however they are written as "VDD!" and "VSS!" in all std cells schematics. So what is the difference between "VDD" and "VDD!" ?

Thanks

Parents
  • oAwad

    Hello Andrew,

    Thank you for your reply. I can't find any VDD or VSS in the exported verliog netlist without any attributes ("saveNetlist design.v"), so I don't know if this will be ok in verilog import in Virtuoso.

    I'm using IC614 (sorry for being outdated). Here is my .ihdlParamFile:

    DirLabel =/root/Desktop/AES128bits/encounter

    Target Library = NangateOpenCellLibrary

    Reference Libraries =NangateOpenCellLibrary

    Verilog Design Files = design.v

    -y Options =

    Library Extn. =

    -v Options =

    -f Options =

    Ignore Modules File =

    Import Modules File =

    Log File =./verilogIn.log

    Work Area =/tmp

    Power Net =VDD!

    Ground Net =VSS!

    Global Signals =

    Net Expression Property Name for Power Net =vdd

    Net Expression Property Name for Ground Net =gnd

    Create Net Expression =false

    Connect By Name Nets =

    Import Modules That Match Existing Target Library Cells =false

    Verilog Cell Modules =Create Symbol Only

    Verilog Structural Modules View =schematic

    Functional View Name =functional

    Netlist View Name =netlist

    Schematic View Name =schematic

    Symbol View Name =symbol

    Name Map Table = ./verilogIn.map.table

    Sheet Size =none

    Pin Placement Flag =Left and Right Sides

    Pin Placement File =

    Label Size =0.062500

    Maximum Number Of Rows =1024

    Maximum Number of Columns =1024

    Line-Line Spacing =   0.20000

    Line-Component Spacing =   0.50000

    Density Level =0

    Full Place and Route =true

    Fast labels =false

    Minimize Cross Over =false

    Generate Square Schematics =true

    Extract Schematics =true

    Ignore Extra Pins =false

    No Dummy Nets In Netlist View =false

    Verbose =false

    Generate Snap Space Properties =true

    Through CellView Library =basic

    Through CellView Cell =cds_thru

    Through CellView View =symbol

    Continuous Assignment CellView Library =basic

    Continuous Assignment CellView Cell =patch

    Continuous Assignment CellView View =symbol

    Pre Compiled Library =

    Destination IR Lib =

    ViewName for IR Library =hdl

    Only Compile a Verilog Library =false

    Can you tell me what to change ?

Reply
  • oAwad

    Hello Andrew,

    Thank you for your reply. I can't find any VDD or VSS in the exported verliog netlist without any attributes ("saveNetlist design.v"), so I don't know if this will be ok in verilog import in Virtuoso.

    I'm using IC614 (sorry for being outdated). Here is my .ihdlParamFile:

    DirLabel =/root/Desktop/AES128bits/encounter

    Target Library = NangateOpenCellLibrary

    Reference Libraries =NangateOpenCellLibrary

    Verilog Design Files = design.v

    -y Options =

    Library Extn. =

    -v Options =

    -f Options =

    Ignore Modules File =

    Import Modules File =

    Log File =./verilogIn.log

    Work Area =/tmp

    Power Net =VDD!

    Ground Net =VSS!

    Global Signals =

    Net Expression Property Name for Power Net =vdd

    Net Expression Property Name for Ground Net =gnd

    Create Net Expression =false

    Connect By Name Nets =

    Import Modules That Match Existing Target Library Cells =false

    Verilog Cell Modules =Create Symbol Only

    Verilog Structural Modules View =schematic

    Functional View Name =functional

    Netlist View Name =netlist

    Schematic View Name =schematic

    Symbol View Name =symbol

    Name Map Table = ./verilogIn.map.table

    Sheet Size =none

    Pin Placement Flag =Left and Right Sides

    Pin Placement File =

    Label Size =0.062500

    Maximum Number Of Rows =1024

    Maximum Number of Columns =1024

    Line-Line Spacing =   0.20000

    Line-Component Spacing =   0.50000

    Density Level =0

    Full Place and Route =true

    Fast labels =false

    Minimize Cross Over =false

    Generate Square Schematics =true

    Extract Schematics =true

    Ignore Extra Pins =false

    No Dummy Nets In Netlist View =false

    Verbose =false

    Generate Snap Space Properties =true

    Through CellView Library =basic

    Through CellView Cell =cds_thru

    Through CellView View =symbol

    Continuous Assignment CellView Library =basic

    Continuous Assignment CellView Cell =patch

    Continuous Assignment CellView View =symbol

    Pre Compiled Library =

    Destination IR Lib =

    ViewName for IR Library =hdl

    Only Compile a Verilog Library =false

    Can you tell me what to change ?

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