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import physical verilog netlist in Virtuoso

oAwad

I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command:

-phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple supply voltages.

-includePowerGround:    Includes power and ground connections in the netlist file.

-includePhysicalInst:   Includes physical instances, such as fillers.

WhenI try to import this netlist in Virtuoso, I get these warnings for all std cells:


WARNING (VERILOGIN-111): Cannot connect the terminal VDD in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-111): Cannot connect the terminal VSS in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-551): Number of pins on symbol DFF_X2 in library NangateOpenCellLibrary differ from the number of ports in
the HDL module description.

When I open the symbol of DFF_X2, there is no VDD and VSS symbol, so should I update the symbol of all std cells manually to have the VDD and VSS symbols ?

(I can find "VDD!" and "VSS!" pins in DFF_X2 schematic but not in its symbol)

Additionally, I get these warnings for FILLER cells:

WARNING (VERILOGIN-72): Could not find the symbol master for the instance FILLER_5. Therefore the functional
view will not have this instance.

And again there is no symbol view for FILLER cells in the std cell library.

Since, all std cells schematics have VDD! and VSS! pins but their symbols don't, was this made so that Virtuoso power these pins virtually without an explicit power source and ground ? or this is wrong and I have to update all symbols manually ?

Finally, power and ground are called "VDD" and "VSS" respectively in my verilog netlist, however they are written as "VDD!" and "VSS!" in all std cells schematics. So what is the difference between "VDD" and "VDD!" ?

Thanks

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  • oAwad
    Hello Andrew,

    I imported the verilog netlist with no attributes ("saveNetlist design.v") with no errors. But when I perform Calibre LVS check, I get errors for every cell stating that the cell in layout have power and ground ports while that in schematic don't.

    Error: Different numbers of ports (see below).
    Error: Power net missing in source. Ground net missing in source.

    I want to run LVS in order to run Calibre PEX after wards to get the SPICE netlist and do post-layout simulations.

    Should I edit all std cells in the library to have power and ground pins in their symbols and them import the verilog netlist using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst" ?
Reply
  • oAwad
    Hello Andrew,

    I imported the verilog netlist with no attributes ("saveNetlist design.v") with no errors. But when I perform Calibre LVS check, I get errors for every cell stating that the cell in layout have power and ground ports while that in schematic don't.

    Error: Different numbers of ports (see below).
    Error: Power net missing in source. Ground net missing in source.

    I want to run LVS in order to run Calibre PEX after wards to get the SPICE netlist and do post-layout simulations.

    Should I edit all std cells in the library to have power and ground pins in their symbols and them import the verilog netlist using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst" ?
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