Behavioral simulation of standard cells: How? (AMS and other attempts fail)

OK, there's a lot of things here, but let me try to give a few pointers and hopefully that will move you forward.

1. An abstract view is for layout purposes. It's a simplified representation of the layout containing pins and blockages and is to help routing tools be able to route more efficiently. It has no use for simulation.
2. The adms_vhdlams view is almost certainly for Mentor's AdvanceMS mixed-signal simulator and won't work with Cadence simulators. We do have a native VHDL-AMS view type which would work with AMS Designer, but you would almost certainly need to copy the model contents (by creating a new view of the right type and then copying the text from one to the other). Unless you have the Mentor integration you may find you can't open the view in Virtuoso because it doesn't know how to handle it. 
3. I suspect that the verilog view is just a stopping view for netlisting purposes and doesn't contain the textual verilog description. Usually if it did the view would have been called something like functional or behavioral instead. You can check that by opening up the verilog view.
4. None of these would work with spectre/APS/XPS anyway, because spectre is a circuit simulator not a logic or mixed-signal simulator. It can understand Verilog-A (which is a subset of Verilog-AMS that only contains the analog portions of the language), but not digital verilog.
5. If you're going to use AMS with the UNL netlister, you are going to need to use a far newer version than IUS8.2. This is from April or May 2009 - and long predates the UNL netlister. You should use INCISIVE151 or INCISIVE152. That's why you had the _amsaIeConnectRulesInfo errors and the IE cards generation failed messages, and almost certainly why it went horribly wrong.
6. You probably don't want to use the AMS Plugin in HED; I'd create the config but then use ADE instead (you can start ADE from HED, or you can launch ADE from the configured schematic window as usual and set the simulator to "ams").
7. If you have picked the view to use as "verilog" in the config, I suspect you'll need to find a verilog definition of the standard cells and include this (via the Simulation->Options->AMS menu)
8. spectreVerilog was end-of-lifed about the time of the last ice age, and it's finally been removed in IC617 (although there are some small vestiges of it remaining, such as the templates for HED). So don't go there... (it was a very old link between spectre and Verilog-XL, which is a good 20 years or so old).

Regards,

Andrew.

Thanks, Andrew, this is so helpful and clarifies a lot! I was not aware of most of the things.

5. - I will try to get INCISIVE152 (as said I also tried incisive/14.20.003 but maybe that's too old as well).

For 3.: You are right, it does only contain the symbol, no Verilog. However, now I found files "behavior/Verilog/*.v" in the standard cell directory - probably to be included as you wrote in 7.

Regarding 4: I know that Spectre is a circuit simulator but in High Performance simulation, there is the choice of digital blocks in "XPS MS". When I select all my (digital) instances of the standard cells as "Digital Subcircuits"/"Digital Instances" I run into the same issue that it runs fast but in turn all the output signals in the results browser are missing ... So at maximum I could use "APS" which is still way too slow.

Regarding 5-6, I got INCISIVE15.20.022! Unfortunately both issues persists.

The fact that I cannot close Cadence any more and get the "unbound variable - _amsaIeConnectRulesInfo" error is annoying but not the most important problem.

However, do you know what *Error* IE cards generation failed means? What are IE cards?
In the ams/config folder I cannot see any more errors except in artSimEnvLog:

generate netlist...
...successful.
create cds_globals...
*Error* IE cards generation failed.
...unsuccessful.
generate netlist...
...successful.
create cds_globals...
*Error* IE cards generation failed.
...unsuccessful.
generate netlist...
...successful.
create cds_globals...
*Error* IE cards generation failed.
...unsuccessful.

and .printhdl:

nchelp: 15.20-s022: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
nchelp: *W,NOVARF: Unable to find an 'hdl.var' file to load.

cds_globals.vams contains:

// Verilog-AMS cds_globals module for top-level cell:
// playground_ams/inv3_ams.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
wire \vdd! ;
wire \vdds! ;
wire \gnds! ;
electrical \gnd! ;
ground \gnd! ;

// Design Variables

endmodule


ie_card.scs (whatever that is) is empty.

(I should also mention that my new test case I created from scratch and only contains one vpulse, res and a cap)

EDIT: To debug further I created a bare new environment with nothing loaded except ic/6.17.701, spectre/16.10.187, INCISIVE/15.20.022 in a new directory; to make sure it has nothing to do with the PDK. Same IE cards error ...

EDIT2: The problem is the ic version. With ic/6.16.110 (and below) it works; with ic/6.17.701 I get the issues described.

itos said:

Regarding 4: I know that Spectre is a circuit simulator but in High Performance simulation, there is the choice of digital blocks in "XPS MS". When I select all my (digital) instances of the standard cells as "Digital Subcircuits"/"Digital Instances" I run into the same issue that it runs fast but in turn all the output signals in the results browser are missing ... So at maximum I could use "APS" which is still way too slow.

XPS is a FastSPICE mode, which means it's still transistor level (it's not a logic simulator) but the digital transistors can be accelerated considerably. I wouldn't expect that to be a problem if you've saved the signals you want to see. You probably should follow this up via your support channel (Europractice maybe?).

Anyway, you may well want to pursue an AMS simulation if you have any significant amounts of digital.

The error message reporting in ISR1 of IC617 was problematic, from what I can see from some CCRs, and this was improved in IC617 ISR4 (IC6.1.7.500.4).

I think the issue is probably that either you don't have a library called connectLib in your cds.lib or it's pointing at a version not from the INCISIVE152 release (oh, and you should have run the configure step when installing INCISIVE152).

You might want to add this to your cds.lib:

INCLUDE $(inst_root_with:tools/bin/irun)/tools/inca/files/cds.lib

that should add a bunch of libraries from the INCISIVE installation into your available libraries, including connectLib, which is needed for the connect models (instances of which are known as "Interface Elements", which is what the "IE card" is all about). These control how digital <-> analog conversion is done at the boundaries between the digital and analog domains.

Regards,

Andrew.

Well, there is unfortunately one small thing left: I have a bunch of VEC files which drive my input nets and work perfectly when used in spectre.

Now with AMS, they seem to be ignored; the nets are always at 0V. I figure the simulation files setup is slightly different (hlCheck missing) for AMS in ADE L but I get the message in the output log that my file has been read.

I found your remark on this: community.cadence.com/.../28218
and connected 1fF cap on all input networks to ground. Now I see 0V (instead of "invalid").

I also created a testnet "TEST" with 1M to ground (so definitely no digital network) driven by this vec file:

radix 1
vname TEST
io    i
; waveform parameter setting
tunit 1e-09
slope 0.1
vol   0
voh   1
vil   0
vih   1

; tabular data
0.000000e+00   1
2.000000e+01   0

Is there anything known about vec files that work perfectly with the same circuit in spectre but not AMS?

This is a scoping problem. Because of how irun works, you can actually have multiple top-level modules (as  you can tell by the fact there is both the design and the cds_globals module), and so it needs to know which module the signals in the vector file are related to.

The vname entries are normally hierarchical paths with "." as the hierarchy separator. You have to include the top cell name at the beginning though (this is the module name), so if your top level cell (the test bench) was called topCellName you'd have to change it to:

vname topCellName.TEST

I tested this with the vector file you posted with the 1Mohm resistor example, and it solved the problem.

Regards,

Andrew.

Hi itos and somebody who found this post with the same problem

I just would like to add one more solution here.

In ADE, Setup --> Connect rules/IE Setup --> Check Connect Rule/Connect Module Based Setup

Then, it would work. The default one is "Interface Element/IE-card Based Setup (OSS/UNL), and I think this is the reason why the netlister did not work since nothing was setup.

I think maybe in previous versions of IC617, the default  one was not "IE-based".

Regards!