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Behavioral simulation of standard cells: How? (AMS and other attempts fail)

itos

Hi,

I am struggling for many hours with the following: The standard cells in my PDK have the views cmos_sch (transistor level), abstract, adms_vhdlams, verilog.

I would like to perform basic functional testing of basic, custom logic but the transient sim takes forever.

My hope is that abstract, adms_vhdlams or verilog could be used as behavioral model, speeding up the sim by multiple orders of magnitude. However, I have no idea what I am even supposed to do.

I tried the following:

1.) Use the HED to change the views of the cells to abstract and verilog and use Spectre, APS or XPS MS.

In all cases, references to the standard cells do NOT appear in the netlist. Subcircuits containing only standard cells become empty. Hence, the result browser does barely contain any signals and the one it contains are zero.
I am not sure if this is supposed to be the case or not.
Maybe the View List or Stop List needs to be modified? (I tried adding "verilog" to both without success)

If I set the views to adms_vhdlams, then I get an error like:

    ERROR (SFE-23): "input.scs" 22: The instance `I0' is referencing an undefined model or subcircuit, `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)'. Either include the file containing the definition of `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)', or define `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)' before running the simulation.

2.) Using AMS. My normal setup uses ic/6.17.701 and spectre/16.10.187; now I additionally load ius/8.20.006. I again use HED to create a new config and use AMS as a template. I select Plugins -> AMS and AMS -> Initialize.

Now weird things start already because I cannot close the HED any more, nor the CIW (I can only kill virtuoso). An attempt to close either just results in:

*Error* eval: unbound variable - _amsaIeConnectRulesInfo

In any case, I can continue by selecting opening the schematic/ADE L with the config and running the sim with AMS. However, then I get the following error in the CIW:

[...]
---------- End of netlist configuration information   ----------
INFO (VLOGNET-80): The library 'playground_ams', cell 'inv2_ams', and view 'config' has been netlisted successfully.

End netlisting Mar 22 00:19:51 2017
INFO (AMS-1243): AMS OSSN netlisting has completed successfully.
To view the modules, choose Simulation->Netlist->Display.
      ...successful.
create cds_globals...
*Error* IE cards generation failed.
      ...unsuccessful.
      
I tried the same with incisive/14.20.003; or even without either; same results.

3.) Use again HED and pick spectreVerilog as template. However, when opening ADE L, I cannot choose spectreVerilog as simulator. I do not know which configuration/package is necessary to make this visible.


Any ideas of either of these questions/problems??

Thank you!














Parents

  • OK, there's a lot of things here, but let me try to give a few pointers and hopefully that will move you forward.

    1. An abstract view is for layout purposes. It's a simplified representation of the layout containing pins and blockages and is to help routing tools be able to route more efficiently. It has no use for simulation.
    2. The adms_vhdlams view is almost certainly for Mentor's AdvanceMS mixed-signal simulator and won't work with Cadence simulators. We do have a native VHDL-AMS view type which would work with AMS Designer, but you would almost certainly need to copy the model contents (by creating a new view of the right type and then copying the text from one to the other). Unless you have the Mentor integration you may find you can't open the view in Virtuoso because it doesn't know how to handle it. 
    3. I suspect that the verilog view is just a stopping view for netlisting purposes and doesn't contain the textual verilog description. Usually if it did the view would have been called something like functional or behavioral instead. You can check that by opening up the verilog view.
    4. None of these would work with spectre/APS/XPS anyway, because spectre is a circuit simulator not a logic or mixed-signal simulator. It can understand Verilog-A (which is a subset of Verilog-AMS that only contains the analog portions of the language), but not digital verilog.
    5. If you're going to use AMS with the UNL netlister, you are going to need to use a far newer version than IUS8.2. This is from April or May 2009 - and long predates the UNL netlister. You should use INCISIVE151 or INCISIVE152. That's why you had the _amsaIeConnectRulesInfo errors and the IE cards generation failed messages, and almost certainly why it went horribly wrong.
    6. You probably don't want to use the AMS Plugin in HED; I'd create the config but then use ADE instead (you can start ADE from HED, or you can launch ADE from the configured schematic window as usual and set the simulator to "ams").
    7. If you have picked the view to use as "verilog" in the config, I suspect you'll need to find a verilog definition of the standard cells and include this (via the Simulation->Options->AMS menu)
    8. spectreVerilog was end-of-lifed about the time of the last ice age, and it's finally been removed in IC617 (although there are some small vestiges of it remaining, such as the templates for HED). So don't go there... (it was a very old link between spectre and Verilog-XL, which is a good 20 years or so old).

    Regards,

    Andrew.

Reply

  • OK, there's a lot of things here, but let me try to give a few pointers and hopefully that will move you forward.

    1. An abstract view is for layout purposes. It's a simplified representation of the layout containing pins and blockages and is to help routing tools be able to route more efficiently. It has no use for simulation.
    2. The adms_vhdlams view is almost certainly for Mentor's AdvanceMS mixed-signal simulator and won't work with Cadence simulators. We do have a native VHDL-AMS view type which would work with AMS Designer, but you would almost certainly need to copy the model contents (by creating a new view of the right type and then copying the text from one to the other). Unless you have the Mentor integration you may find you can't open the view in Virtuoso because it doesn't know how to handle it. 
    3. I suspect that the verilog view is just a stopping view for netlisting purposes and doesn't contain the textual verilog description. Usually if it did the view would have been called something like functional or behavioral instead. You can check that by opening up the verilog view.
    4. None of these would work with spectre/APS/XPS anyway, because spectre is a circuit simulator not a logic or mixed-signal simulator. It can understand Verilog-A (which is a subset of Verilog-AMS that only contains the analog portions of the language), but not digital verilog.
    5. If you're going to use AMS with the UNL netlister, you are going to need to use a far newer version than IUS8.2. This is from April or May 2009 - and long predates the UNL netlister. You should use INCISIVE151 or INCISIVE152. That's why you had the _amsaIeConnectRulesInfo errors and the IE cards generation failed messages, and almost certainly why it went horribly wrong.
    6. You probably don't want to use the AMS Plugin in HED; I'd create the config but then use ADE instead (you can start ADE from HED, or you can launch ADE from the configured schematic window as usual and set the simulator to "ams").
    7. If you have picked the view to use as "verilog" in the config, I suspect you'll need to find a verilog definition of the standard cells and include this (via the Simulation->Options->AMS menu)
    8. spectreVerilog was end-of-lifed about the time of the last ice age, and it's finally been removed in IC617 (although there are some small vestiges of it remaining, such as the templates for HED). So don't go there... (it was a very old link between spectre and Verilog-XL, which is a good 20 years or so old).

    Regards,

    Andrew.

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