Sampled point inaccuracy in AMS simulation

Hello,

I am trying to simulate a Verilog-AMS model of an ideal ADC, together with some Verilog-A and Verilog modules. Versions of the tools I use:

virtuoso : IC6-1-6.64b.500.11

spectre : 13.1.1.292.isr12 64bit

irun(64) : 14.10-s008

Netlist and run mode: AMS Unified Netlister with irun

Output log gives the following simulator parameters:

Important parameter values:
start = 0 s
outputstart = 0 s
stop = 1.89433 us
step = 1.89433 ns
maxstep = 18.9433 ns
ic = all
useprevic = no
skipdc = no
reltol = 100e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

The Verilog-AMS code for the ADC looks like this:

always @ (posedge dclk) begin
   rin = V(vin) ;
   sample = V(vin) ;
   for (i=`NBITS-1; i>=0; i=i-1) begin
      is_over = (sample > halfref);
      if (is_over) sample = sample - halfref;
      sample = 2.0 * sample;
      dout[i] = is_over;
   end
end

Here, dclk and dout are of logic discipline, and vin is of electrical discipline. It works correctly except for some samples.

Here is a particular sampling instant:

There is a difference of 40 mV between V(vin) and the sampled value rin, which is unacceptable for my application.

I also checked the computed points and observed a cluster of points near the rising clock edge, but the sampled value occurs quite far away from this edge:

The time difference between those two samples is more than 4ps, but I use a timescale precision of 1fs in all my Verilog and Verilog-AMS modules in the netlist, so I have no idea where this error comes from.

Do you have any idea on the cause and solution of this abnormality? Or an advice on how to further debug?

Thanks in advance!

Arda