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Sampled point inaccuracy in AMS simulation

auran

Hello,

I am trying to simulate a Verilog-AMS model of an ideal ADC, together with some Verilog-A and Verilog modules. Versions of the tools I use:

virtuoso : IC6-1-6.64b.500.11

spectre : 13.1.1.292.isr12 64bit

irun(64) : 14.10-s008

Netlist and run mode: AMS Unified Netlister with irun

Output log gives the following simulator parameters:

Important parameter values:
start = 0 s
outputstart = 0 s
stop = 1.89433 us
step = 1.89433 ns
maxstep = 18.9433 ns
ic = all
useprevic = no
skipdc = no
reltol = 100e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

The Verilog-AMS code for the ADC looks like this:

always @ (posedge dclk) begin
   rin = V(vin) ;
   sample = V(vin) ;
   for (i=`NBITS-1; i>=0; i=i-1) begin
      is_over = (sample > halfref);
      if (is_over) sample = sample - halfref;
      sample = 2.0 * sample;
      dout[i] = is_over;
   end
end

Here, dclk and dout are of logic discipline, and vin is of electrical discipline. It works correctly except for some samples.

Here is a particular sampling instant:

There is a difference of 40 mV between V(vin) and the sampled value rin, which is unacceptable for my application.

I also checked the computed points and observed a cluster of points near the rising clock edge, but the sampled value occurs quite far away from this edge:

The time difference between those two samples is more than 4ps, but I use a timescale precision of 1fs in all my Verilog and Verilog-AMS modules in the netlist, so I have no idea where this error comes from.

Do you have any idea on the cause and solution of this abnormality? Or an advice on how to further debug?

Thanks in advance!

Arda

Parents
  • auran

    Hello Andrew, thanks for your reply.

    Here is a simple test case which includes:

    -the ADC model

    -two ideal voltage sources for input sine and clock

    -an electrical to logic interface to create a discrete-event clock from the voltage source.

    -the netlist for test bench that combines the above

    -the ocean script generated from the ADE L window

    Another strange behavior I notice is that the errors occur at different times for each different run of the same netlist.

    Best,

    Arda

    ADC:

    //Verilog-AMS HDL for "tiadc_ams", "interface_adc_10bit" "verilogams"
    `include "constants.vams"
    `include "disciplines.vams"

    `define NBITS 10
    `timescale 1s/1fs

    module test_timestep_interface_adc_10bit(vin, dclk, dout);

    input vin;
    input dclk;
    output reg [`NBITS-1:0] dout;

    //disciplines
    electrical vin;
    logic dclk;
    logic [`NBITS-1:0] dout;

    real vref;
    reg [`NBITS-1:0] dout_reg [0:127]; //the input sine period is set to repeat every 128 samples
    integer counter;
    integer ok, error;

    real rin, sample, halfref;
    reg is_over;

    integer i;

    //initialize
    initial begin
    dout = 0;
    vref = 1.0;
    halfref = vref/2.0;
    counter = 0;
    ok = 0;
    error = 0;
    end

    //A/D conversion
    always @ (posedge dclk) begin
    rin = V(vin) ;
    sample = V(vin);
    for (i=`NBITS-1; i>=0; i=i-1) begin
    is_over = (sample > halfref);
    if (is_over) sample = sample - halfref;
    sample = 2.0 * sample;
    dout[i] = is_over;
    end
    //store expected values and inform in case of inequality
    if ((ok == 1) && (dout_reg[counter] != dout)) begin
    error = 1;
    end
    if (ok != 1) dout_reg[counter] = dout;
    if (counter == 127) ok = 1; //expected values are stored
    counter = (counter + 1)%128;
    end
    endmodule

    Electrical to logic interface:

    //Verilog-AMS HDL for "tiadc_ams", "interface_e2l" "verilogams"

    `include "constants.vams"
    `include "disciplines.vams"

    `timescale 1s/1fs

    module interface_e2l( vin, dout );
    input vin;
    output reg dout;

    //disciplines
    electrical vin;
    logic dout;

    parameter real vtrans = 0.5 from [0:inf);
    parameter integer logic_out_initial = 1 from [0:1];

    initial begin
    dout = logic_out_initial;
    end

    always @ (cross(V(vin) - vtrans, 1)) dout = 1;
    always @ (cross(V(vin) - vtrans, -1)) dout = 0;

    endmodule

    Netlist:

    ////////////////////////////////////////////////////////////////////////
    // PLEASE DO NOT EDIT OR COMPILE THIS FILE.
    // IT IS MEANT FOR VIEWING PURPOSE ONLY.
    //
    // All files for configuration: (tiadc_ams test_timestep config)
    ////////////////////////////////////////////////////////////////////////

    // AMS netlist generated by the AMS Unified netlister
    // IC subversion: IC6.1.6-64b.500.11
    // IUS version: 15.10-s021
    // Copyright(C) 2005-2009, Cadence Design Systems, Inc
    // User: auran Pid: 32612
    // Design library name: tiadc_ams
    // Design cell name: test_timestep
    // Design view name: config
    // Solver: Spectre

    `include "disciplines.vams"
    `include "userDisciplines.vams"
    // HDL file - tiadc_ams, interface_e2l, verilogams.
    // HDL file - tiadc_ams, test_timestep_interface_adc_10bit, verilogams.
    // Library - tiadc_ams, Cell - test_timestep, View - schematic
    // LAST TIME SAVED: Apr 2 23:37:21 2017
    // NETLIST TIME: Apr 3 00:10:34 2017

    `worklib tiadc_ams
    `view schematic

    `timescale 1ns / 1ns
    (* cds_ams_schematic *)

    module test_timestep ( );
    wire [9:0] DOUT;
    wire IN;
    wire DCLK;
    wire CLK_MASTER;
    test_timestep_interface_adc_10bit ADC (.dclk( DCLK ), .dout( DOUT ), .vin( IN ));
    interface_e2l #(.logic_out_initial(0)) I2 (.dout( DCLK ), .vin( CLK_MASTER ));
    vsource #(.type("sine"), .sinedc(0.5), .ampl(0.91/2), .freq(12e+9*509/1024)) VIN_SINE (IN, cds_globals.\gnd! );
    vsource #(.type("pulse"), .val0(0), .val1(1), .period(1/(12e+9/16)), .delay(0), .rise(1/(12e+9/16)/100), .fall(1/(12e+9/16)/100)) VCLK_MASTER (CLK_MASTER, cds_globals.\gnd! );

    endmodule
    `noworklib
    `noview
    // Verilog-AMS cds_globals module for top-level cell:
    // tiadc_ams/test_timestep.
    // Generated by ADE.
    // Cadence Design Systems, Inc.

    // This is an autoGenerated file, any changes done to this file may get lost.

    `include "disciplines.vams"
    `include "userDisciplines.vams"

    module cds_globals;

    // Global Signals
    electrical \gnd! ;
    ground \gnd! ;

    // Design Variables

    endmodule

    // This is the Cadence AMS Designer(R) analog simulation control file.
    // It specifies the options and analyses for the Spectre analog solver.

    simulator lang=spectre

    global 0

    simulatorOptions options temp=27 tnom=27 scale=1.0 scalem=1.0 reltol=1e-7 \
    vabstol=1e-6 iabstol=1e-12 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 pivrel=1e-3 checklimitdest=psf

    tran tran stop=853.333333e-7 errpreset=conservative save=none \
    write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5

    finalTimeOP info what=oppoint where=rawfile

    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile

    # This is the NC-SIM(R) probe command file
    # used in the AMS-ADE integration.


    #
    # Database settings
    #
    if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
    database -open ams_database -into ${AMS_RESULTS_DIR} -default

    #
    # Probe settings
    #
    probe -create -emptyok -database ams_database -all -memories -depth all {test_timestep}
    probe -create -emptyok -database ams_database -all -memories cds_globals
    probe -create -emptyok -database ams_database -aicms -all {test_timestep}

    Ocean script:

    simulator( 'ams )
    solver( 'Spectre )
    design( "RUNDIR/simulation/test_timestep/ams/config/netlist/netlist")
    ocnAmsSetUnlNetlister()
    resultsDir( "RUNDIR/simulation/test_timestep/ams/config" )
    globalSignal(?name "gnd!" ?lang "CDBA" ?wireType "wire" ?discipline "" ?ground "YES")
    definitionFile(
    "models.scs"
    )
    analysis('tran ?stop "853.333333e-7" ?errpreset "conservative" )
    envOption(
    'netlisterMode "AMS-UNL"
    )
    option( 'reltol "1e-7"
    )
    saveOption( ?probeMemories t )
    saveOption( 'currents "none" )
    saveOption( 'cmSave "all" )
    saveOption( 'netLevelsToSave "all" )
    saveOption( 'save "all" )
    temp( 27 )
    run()

Reply
  • auran

    Hello Andrew, thanks for your reply.

    Here is a simple test case which includes:

    -the ADC model

    -two ideal voltage sources for input sine and clock

    -an electrical to logic interface to create a discrete-event clock from the voltage source.

    -the netlist for test bench that combines the above

    -the ocean script generated from the ADE L window

    Another strange behavior I notice is that the errors occur at different times for each different run of the same netlist.

    Best,

    Arda

    ADC:

    //Verilog-AMS HDL for "tiadc_ams", "interface_adc_10bit" "verilogams"
    `include "constants.vams"
    `include "disciplines.vams"

    `define NBITS 10
    `timescale 1s/1fs

    module test_timestep_interface_adc_10bit(vin, dclk, dout);

    input vin;
    input dclk;
    output reg [`NBITS-1:0] dout;

    //disciplines
    electrical vin;
    logic dclk;
    logic [`NBITS-1:0] dout;

    real vref;
    reg [`NBITS-1:0] dout_reg [0:127]; //the input sine period is set to repeat every 128 samples
    integer counter;
    integer ok, error;

    real rin, sample, halfref;
    reg is_over;

    integer i;

    //initialize
    initial begin
    dout = 0;
    vref = 1.0;
    halfref = vref/2.0;
    counter = 0;
    ok = 0;
    error = 0;
    end

    //A/D conversion
    always @ (posedge dclk) begin
    rin = V(vin) ;
    sample = V(vin);
    for (i=`NBITS-1; i>=0; i=i-1) begin
    is_over = (sample > halfref);
    if (is_over) sample = sample - halfref;
    sample = 2.0 * sample;
    dout[i] = is_over;
    end
    //store expected values and inform in case of inequality
    if ((ok == 1) && (dout_reg[counter] != dout)) begin
    error = 1;
    end
    if (ok != 1) dout_reg[counter] = dout;
    if (counter == 127) ok = 1; //expected values are stored
    counter = (counter + 1)%128;
    end
    endmodule

    Electrical to logic interface:

    //Verilog-AMS HDL for "tiadc_ams", "interface_e2l" "verilogams"

    `include "constants.vams"
    `include "disciplines.vams"

    `timescale 1s/1fs

    module interface_e2l( vin, dout );
    input vin;
    output reg dout;

    //disciplines
    electrical vin;
    logic dout;

    parameter real vtrans = 0.5 from [0:inf);
    parameter integer logic_out_initial = 1 from [0:1];

    initial begin
    dout = logic_out_initial;
    end

    always @ (cross(V(vin) - vtrans, 1)) dout = 1;
    always @ (cross(V(vin) - vtrans, -1)) dout = 0;

    endmodule

    Netlist:

    ////////////////////////////////////////////////////////////////////////
    // PLEASE DO NOT EDIT OR COMPILE THIS FILE.
    // IT IS MEANT FOR VIEWING PURPOSE ONLY.
    //
    // All files for configuration: (tiadc_ams test_timestep config)
    ////////////////////////////////////////////////////////////////////////

    // AMS netlist generated by the AMS Unified netlister
    // IC subversion: IC6.1.6-64b.500.11
    // IUS version: 15.10-s021
    // Copyright(C) 2005-2009, Cadence Design Systems, Inc
    // User: auran Pid: 32612
    // Design library name: tiadc_ams
    // Design cell name: test_timestep
    // Design view name: config
    // Solver: Spectre

    `include "disciplines.vams"
    `include "userDisciplines.vams"
    // HDL file - tiadc_ams, interface_e2l, verilogams.
    // HDL file - tiadc_ams, test_timestep_interface_adc_10bit, verilogams.
    // Library - tiadc_ams, Cell - test_timestep, View - schematic
    // LAST TIME SAVED: Apr 2 23:37:21 2017
    // NETLIST TIME: Apr 3 00:10:34 2017

    `worklib tiadc_ams
    `view schematic

    `timescale 1ns / 1ns
    (* cds_ams_schematic *)

    module test_timestep ( );
    wire [9:0] DOUT;
    wire IN;
    wire DCLK;
    wire CLK_MASTER;
    test_timestep_interface_adc_10bit ADC (.dclk( DCLK ), .dout( DOUT ), .vin( IN ));
    interface_e2l #(.logic_out_initial(0)) I2 (.dout( DCLK ), .vin( CLK_MASTER ));
    vsource #(.type("sine"), .sinedc(0.5), .ampl(0.91/2), .freq(12e+9*509/1024)) VIN_SINE (IN, cds_globals.\gnd! );
    vsource #(.type("pulse"), .val0(0), .val1(1), .period(1/(12e+9/16)), .delay(0), .rise(1/(12e+9/16)/100), .fall(1/(12e+9/16)/100)) VCLK_MASTER (CLK_MASTER, cds_globals.\gnd! );

    endmodule
    `noworklib
    `noview
    // Verilog-AMS cds_globals module for top-level cell:
    // tiadc_ams/test_timestep.
    // Generated by ADE.
    // Cadence Design Systems, Inc.

    // This is an autoGenerated file, any changes done to this file may get lost.

    `include "disciplines.vams"
    `include "userDisciplines.vams"

    module cds_globals;

    // Global Signals
    electrical \gnd! ;
    ground \gnd! ;

    // Design Variables

    endmodule

    // This is the Cadence AMS Designer(R) analog simulation control file.
    // It specifies the options and analyses for the Spectre analog solver.

    simulator lang=spectre

    global 0

    simulatorOptions options temp=27 tnom=27 scale=1.0 scalem=1.0 reltol=1e-7 \
    vabstol=1e-6 iabstol=1e-12 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 pivrel=1e-3 checklimitdest=psf

    tran tran stop=853.333333e-7 errpreset=conservative save=none \
    write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5

    finalTimeOP info what=oppoint where=rawfile

    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile

    # This is the NC-SIM(R) probe command file
    # used in the AMS-ADE integration.


    #
    # Database settings
    #
    if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
    database -open ams_database -into ${AMS_RESULTS_DIR} -default

    #
    # Probe settings
    #
    probe -create -emptyok -database ams_database -all -memories -depth all {test_timestep}
    probe -create -emptyok -database ams_database -all -memories cds_globals
    probe -create -emptyok -database ams_database -aicms -all {test_timestep}

    Ocean script:

    simulator( 'ams )
    solver( 'Spectre )
    design( "RUNDIR/simulation/test_timestep/ams/config/netlist/netlist")
    ocnAmsSetUnlNetlister()
    resultsDir( "RUNDIR/simulation/test_timestep/ams/config" )
    globalSignal(?name "gnd!" ?lang "CDBA" ?wireType "wire" ?discipline "" ?ground "YES")
    definitionFile(
    "models.scs"
    )
    analysis('tran ?stop "853.333333e-7" ?errpreset "conservative" )
    envOption(
    'netlisterMode "AMS-UNL"
    )
    option( 'reltol "1e-7"
    )
    saveOption( ?probeMemories t )
    saveOption( 'currents "none" )
    saveOption( 'cmSave "all" )
    saveOption( 'netLevelsToSave "all" )
    saveOption( 'save "all" )
    temp( 27 )
    run()

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